3.0 Applications Information (Continued)
Mode 1 and Mode 4
Mode 2 and Mode 5
1
V
OS3
e
a
b
V
V
1 H
OLP
R2
1
OS(N)
OS1
e
Q
Q
a
c
OS1
# ÀÀ ÀÀJ
V
1
1
V
OS(N)
a
R
1
R2/R4
#
J
p
e
e
V
V
V
V
OS(BP)
OS3
1
V
OS3
b
a
b
V
OS2
V
OS2
:
OS(LP)
OS(N)
a
a
R2/R4
R4/R2 Q 1
0
Mode 1a
e
R
R1//R3//R4
p
1
V
OS3
e
a
b
V
(N.INV.BP)
OS
1
V
OS1
e
e
V
V
V
V
OS(BP)
OS3
Q
Q
# J
b
V
OS(LP)
OS(N)
OS2
e
e
V
V
(INV.BP)
V
V
OS
OS3
Mode 3
b
(N.INV.BP)
OS
V
OS2
OS(LP)
e
e
e
V
V
V
V
V
V
OS(HP)
OS(BP)
OS(LP)
OS2
OS3
R4
R4
a
b
V
1
OS1
OS2
R
(
R2
# J
Ð
p
R4
R3
b
V
OS3
# J
e
Rp
R1//R2//R3
TL/H/10399–30
FIGURE 19. MF10 Offset Voltage Sources
TL/H/10399–31
FIGURE 20. Method for Trimming V
OS
16
NSC [ National Semiconductor ]
