3.0 Applications Information (Continued)
TL/H/10399–28
TL/H/10399–27
(b) Voltage Regulator
TL/H/10399–29
(a) Resistive Divider with
Decoupling Capacitor
(c) Operational Amplifier
with Divider
Va
2
FIGURE 18. Three Ways of Generating
for Single-Supply Operation
3.2 SINGLE SUPPLY OPERATION
10 will have a 20 dB peak in its amplitude response at f . If
O
the nominal gain of the filter H
f
is equal to 1, the gain at
OLP
will be 10. The maximum input signal at f must therefore
The MF10 can also operate with a single-ended power sup-
ply. Figure 17 shows the example filter with a single-ended
O
O
when the circuit is operated on
a
a
be less than 800 mV
p–p
g
5V supplies.
power supply. V
and V
positive power supply (8V to 14V), and V
are again connected to the
b
D
A
D
b
and V
are
A
connected to ground. The A
pin must be tied to Va/2
Also note that one output can have a reasonable small volt-
age on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7). The notch
GND
for single supply operation. This half-supply point should be
very ‘‘clean’’, as any noise appearing on it will be treated as
an input to the filter. It can be derived from the supply volt-
age with a pair of resistors and a bypass capacitor (Figure
18a), or a low-impedance half-supply voltage can be made
using a three-terminal voltage regulator or an operational
amplifier (Figures 18b and 18c). The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 mF.
output will be very small at f , so it might appear safe to
O
apply a large signal to the input. However, the bandpass will
have its maximum gain at f and can clip if overdriven. If
O
one output clips, the performance at the other outputs will
be degraded, so avoid overdriving any filter section, even
ones whose outputs are not being directly used. Accompa-
nying Figures 7 through 15 are equations labeled ‘‘circuit
dynamics’’, which relate the Q and the gains at the various
outputs. These should be consulted to determine peak cir-
cuit gains and maximum allowable signals for a given appli-
cation.
3.4 OFFSET VOLTAGE
The MF10’s switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator. Figure 19
shows an equivalent circuit of the MF10 from which the out-
put DC offsets can be calculated. Typical values for these
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF10, like
that of any active filter, is limited by the power supply volt-
ages used. The amplifiers in the MF10 are able to swing to
within about 1V of the supplies, so the input signals must be
kept small enough that none of the outputs will exceed
offsets with S
tied to Va are:
A/B
e
e
g
V
opamp offset
5 mV
os1
@
150 mV 50:1
@
70 mV 50:1
@
300 mV 100:1
@
140 mV 100:1
e b
e b
b
b
V
os2
V
os3
g
these limits. If the MF10 is operating on 5V, for example,
the outputs will clip at about 8 V . The maximum input
p–p
voltage multiplied by the filter gain should therefore be less
than 8 V
When S
is tied to Vb, V
will approximately halve. The
os2
A/B
DC offset at the BP output is equal to the input offset of the
.
p–p
lowpass integrator (V ). The offsets at the other outputs
os3
depend on the mode of operation and the resistor ratios, as
described in the following expressions.
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Figure 6). As an example, a lowpass filter with a Q of
15
NSC [ National Semiconductor ]
