LP3971
I
2
C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, V
IN
= 3.6V. Typical values and limits appearing in normal type apply for T
J
= 25˚C. Limits appearing in
boldface
type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and (Note 9)
Symbol
V
IL
V
IH
V
OL
I
OL
F
CLK
t
BF
t
HOLD
t
CLKLP
t
CLKHP
t
SU
t
DATAHLD
t
CLKSU
T
SU
T
TRANS
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
Low Level Output Current
Clock Frequency
Bus-Free Time Between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
CLK High Period
Set Up Time Repeated Start Condition
Data Hold Time
Data Set Up Time
Set Up Time for Start Condition
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input Filter
of Both DATA & CLK Signals
Conditions
V
OL
= 0.4V (Note 14)
1.3
0.6
1.3
0.6
0.6
0
100
0.6
50
Min
−0.5
0.7 V
RTC
0
3.0
400
Typ
Max
0.3 V
RTC
V
RTC
0.2 V
TRC
mA
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
Units
V
Note 1:
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pin.
Note 3:
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ
JA
), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θ
JA
x PD-MAX).
Note 4:
Junction-to-ambient thermal resistance (θ
JA
) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation
exists, special care must be paid to thermal dissipation issues in board design. The value of
θ
JA
of this product can vary significantly, depending on PCB material,
layout, and environmental conditions. In applications where high maximum power dissipation exists (high V
IN
, high I
OUT
), special care must be paid to thermal
dissipation issues. For more information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and
Power Dissipation
section of this datasheet.
Note 5:
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7). The machine model is a 200 pF
capacitor discharged directly into each pin. (EAIJ)
Note 6:
All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production
tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 7:
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
Note 8:
Back-up battery charging current is programmable via the I
2
C compatible interface. Refer to the Application Section for more information.
Note 9:
The I
2
C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ range.
Note 10:
LDO_RTC voltage can track LDO1 (I/O) Voltage. Refer to LP3971 Controls Section for more information.
Note 11:
V
IN
minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages below the minimum
input operating voltage.
Note 12:
The input voltage range recommended for ideal applications performance for the specified output voltages is given below:
V
IN
= 2.7V to 5.5V for 0.80V
<
V
OUT
<
1.8V
V
IN
= (V
OUT
+ 1V) to 5.5V for 1.8V
≤
V
OUT
≤
3.3V
Note 13:
Test condition: for V
OUT
less than 2.7V, V
IN
= 3.6V; for V
OUT
greater than or equal to 2.7V, V
IN
= V
OUT
+ 1V.
Note 14:
This electrical specification is guaranteed by design.
Note 15:
An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 16:
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
11
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
