LP3966ES-ADJ 参数 Datasheet PDF下载

LP3963/LP3966

Typical Application Circuits

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DS101267-34

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Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional sta-

bility margin.

*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section

for more information.

Block Diagram LP3963

DS101267-3

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