LP3963/LP3966
Electrical Characteristics
LP3963/LP3966
(Continued)
Limits in standard typeface are for T
J
= 25˚C, and limits in
boldface type
apply over the
full operating temperature
range.
Unless otherwise specified: V
IN
= V
O(NOM)
+ 1.5V, I
L
= 10 mA, C
OUT
=10µF, V
SD
= V
IN
-0.3V.
Symbol
SHUTDOWN INPUT
V
EF(Sat)
Td
I
lk
I
max
Error Flag Saturation
Flag Reset Delay
Error Flag Pin Leakage
Current
Error Flag Pin Sink
Current
V
Error
=
0.5V
I
sink
= 100µA
0.02
1
1
1
0.1
V
µs
nA
mA
Parameter
Conditions
Typ(Note
4)
LP3963/6
(Note 5)
Min
Max
Units
AC PARAMETERS
V
IN
= V
OUT
+ 1.5V
C
OUT
= 100uF
V
OUT
= 3.3V
V
IN
= V
OUT
+ 0.3V
C
OUT
= 100uF
V
OUT
= 3.3V
f = 120Hz
BW = 10Hz – 100kHz
BW = 300Hz – 300kHz
60
PSRR
Ripple Rejection
40
dB
ρ
n(l/f
e
n
Output Noise Density
Output Noise Voltage
(rms)
0.8
150
100
µV
µV
(rms)
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-
tended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Charateristics. The guar-
anteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at
θ
jA
= 50˚C/W
(with 0.5in
2
, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at
θ
jA
= 60˚C/W (with
0.5in
2
, 1oz. copper area), junction-to-ambient.
Note 3:
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4:
Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 5:
Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 6:
If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground.
Note 7:
The output PMOS structure contains a diode between the V
IN
and V
OUT
terminals. This diode is normally reverse biased. This diode will get forward biased
if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp
of peak current.
Note 8:
Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load
regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only
the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.
Note 9:
Error Flag threshold and hysteresis are specified as percentage of regulated output voltage.
Note 10:
Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage speci-
fication applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since
the minimum input voltage is 2.5V.
Note 11:
This specification has been tested for −40˚C
≤
T
J
≤
85˚C since the temperature rise of the device is negligible under shutdown conditions.
7
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