LM555
Applications Information
(Continued)
00785117
V
CC
= 5V
TIME = 20µs/DIV.
R
1
= 47kΩ
R
2
= 100kΩ
R
E
= 2.7 kΩ
C = 0.01 µF
Top Trace: Input 3V/Div.
Middle Trace: Output 5V/Div.
Bottom Trace: Capacitor Voltage 1V/Div.
00785118
FIGURE 14. 50% Duty Cycle Oscillator
Note that this circuit will not oscillate if R
B
is greater than 1/2
R
A
because the junction of R
A
and R
B
cannot bring pin 2
down to 1/3 V
CC
and trigger the lower comparator.
ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1µF in par-
allel with 1µF electrolytic.
Lower comparator storage time can be as long as 10µs
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10µs minimum.
Delay time reset to output is 0.47µs typical. Minimum reset
pulse width must be 0.3µs, typical.
Pin 7 current switches within 30ns of the output (pin 3)
voltage.
FIGURE 13. Linear Ramp
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors R
A
and R
B
may be
connected as in
The time period for the output
high is the same as previous, t
1
= 0.693 R
A
C. For the output
low it is t
2
=
Thus the frequency of oscillation is
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