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LM3485MMX 参数 Datasheet PDF下载

LM3485MMX图片预览
型号: LM3485MMX
PDF下载: 下载PDF文件 查看货源
内容描述: 迟滞PFET降压控制器 [Hysteretic PFET Buck Controller]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 15 页 / 372 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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LM3485
Electrical Characteristics
(Continued)
Specifications in Standard type face are for T
J
= 25˚C, and in
bold type face
apply over the full
Operating Temperature
Range
(T
J
= −40˚C to +125˚C). Unless otherwise specified, V
IN
= 12V, V
ISNS
= V
IN
− 1V, and V
ADJ
= V
IN
− 1.1V. Datasheet
min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol
Parameter
Minimum on time in
current limit
Conditions
V
ISNS
= V
ADJ
+0.1V
V
FB
= 1.0V C
load
on
OUT = 1000pF
4.5
V
IN
35V
Min
Typ
175
Max
Unit
ns
T
ONMIN_CL
%V
FB
/∆V
IN
Feedback Voltage
Line Regulation
0.010
%/V
Note 1:
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2:
The maximum allowable power dissipation is a function of the maximum junction temperature, T
J_MAX
, the junction-to-ambient thermal resistance,
θ
JA
=
240˚C/W, and the ambient temperature, T
A
. The maximum allowable power dissipation at any ambient temperature is calculated using:
P
D_MAX
= (T
J_MAX
- T
A
)/θ
JA
. Exceeding the maximum allowable power dissipation will cause excessive die temperature.
Note 3:
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4:
All limits are guaranteed at room temperature (standard type face) and at
temperature extremes (bold type face).
All room temperature limits are 100%
tested. All limits at
temperature extremes
are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate
Average Outgoing Quality Level (AOQL).
Note 5:
Typical numbers are at 25˚C and represent the most likely norm.
Note 6:
The V
FB
is the trip voltage at the FB pin when PGATE switches from high to low.
Note 7:
V
CL
= I
CL_ADJ
*
R
ADJ
Note 8:
Bias current flows out from the FB pin.
Note 9:
A 1000pF capacitor is connected between V
IN
and PGATE.
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