before the first Serration pulse occurs, the integrator now
charges the capacitor to a much higher voltage. At the first
serration pulse the integrator output should be between V1
and V2. This would give a high level at the output of the
comparator with V1 as one of its inputs. This high is clocked
into the “D” flip-flop by the falling edge of the serration pulse
(remember the sync signal is inverted in this section of the
LM1881). The “Q” output of the “D” flip-flop goes through the
OR gate, and sets the R/S flip-flop. The output of the R/S
flip-flop enables the internal oscillator and also clocks the
ODD/EVEN “D” flip-flop. The ODD/EVEN field pulse opera-
tion is covered in the next section. The output of the oscilla-
tor goes to a divide by 8 circuit, thus resetting the R/S
flip-flop after 8 cycles of the oscillator. The frequency of the
oscillator is established by the internal capacitor going to the
oscillator and the external RSET. The “Q” output of the R/S
flip-flop goes to pin 3 and is the actual vertical sync output of
the LM1881. By clocking the “D” flip-flop at the start of the
first serration pulse means that the vertical sync output pulse
starts at this point in time and lasts for eight cycles of the
internal oscillator as shown in Figure 1.
Application Notes (Continued)
COMPOSITE SYNC OUTPUT
The composite sync output, Figure 1(b), is simply a repro-
duction of the signal waveform below the composite video
black level, with the video completely removed. This is ob-
tained by clamping the video signal sync tips to 1.5V DC at
Pin 2 and using a comparator threshold set just above this
voltage to strip the sync signal, which is then buffered out to
Pin 1. The threshold separation from the clamped sync tip is
nominally 70 mV which means that for the minimum input
level of 0.5V (p-p), the clipping level is close to the halfway
point on the sync pulse amplitude (shown by the dashed line
on Figure 1(a). This threshold separation is independent of
the signal amplitude, therefore, for a 2V (p-p) input the
clipping level occurs at 11% of the sync pulse amplitude. The
charging current for the input coupling capacitor is 0.8 mA,
Normally the signal source for the LM1881 is assumed to be
clean and relatively noise-free, but some sources may have
excessive video peaking, causing high frequency video and
chroma components to extend below the black level refer-
ence. Some video discs keep the chroma burst pulse
present throughout the vertical blanking period so that the
burst actually appears on the sync tips for three line periods
instead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input signal.
When the source impedance is low, typically 75Ω, a 620Ω
resistor in series with the source and a 510 pF capacitor to
ground will form a low pass filter with a corner frequency of
500 kHz. This bandwidth is more than sufficient to pass the
sync pulse portion of the waveform; however, any subcarrier
content in the signal will be attenuated by almost 18 dB,
effectively taking it below the comparator threshold. Filtering
will also help if the source is contaminated with thermal
noise. The output waveforms will become delayed from be-
tween 40 ns to as much as 200 ns due to this filter. This
much delay will not usually be significant but it does contrib-
ute to the sync delay produced by any additional signal
processing. Since the original video may also undergo pro-
cessing, the need for time delay correction will depend on
the total system, not just the sync stripper.
How RSET affects the integrator and the internal oscillator is
shown under the Typical Performance Characteristics. The
first graph is “RSET Value Selection vs Vertical Serration
Pulse Separation”. For this graph to be valid, the vertical
sync pulse should last for at least 85% of the horizontal half
line (47% of a full horizontal line). A vertical sync pulse from
any standard should meet this requirement; both NTSC and
PAL do meet this requirement (the serration pulse is the
remainder of the period, 10% to 15% of the horizontal half
line). Remember this pulse is a positive pulse at the integra-
tor but negative in Figure 1. This graph shows how long it
takes the integrator to charge its internal capacitor above V1.
With RSET too large the charging current of the integrator will
be too small to charge the capacitor above V1, thus there will
be no vertical synch output pulse. As mentioned above, RSET
also sets the frequency of the internal oscillator. If the oscil-
lator runs too fast its eight cycles will be shorter than the
vertical sync portion of the composite sync. Under this con-
dition another vertical sync pulse can be generated on one of
the later serration pulse after the divide by 8 circuit resets the
R/S flip-flop. The first graph also shows the minimum RSET
necessary to prevent a double vertical pulse, assuming that
the serration pulses last for only three full horizontal line
periods (six serration pulses for NTSC). The actual pulse
width of the vertical sync pulse is shown in the “Vertical
Pulse Width vs RSET” graph. Using NTSC as an example,
lets see how these two graphs relate to each other. The
Horizontal line is 64 µs long, or 32 µs for a horizontal half
line. Now round this off to 30 µs. In the “RSET Value Selection
vs Vertical Serration Pulse Separation” graph the minimum
resistor value for 30 µs serration pulse separation is about
550 kΩ. Going to the “Vertical Pulse Width vs RSET” graph
one can see that 550 kΩ gives a vertical pulse width of about
180 µs, the total time for the vertical sync period of NTSC (3
horizontal lines). A 550 kΩ will set the internal oscillator to a
frequency such that eight cycles gives a time of 180 µs, just
long enough to prevent a double vertical sync pulse at the
vertical sync output of the LM1881.
VERTICAL SYNC OUTPUT
A vertical sync output is derived by internally integrating the
composite sync waveform (Figure 2). To understand the
generation of the vertical sync pulse, refer to the lower left
hand section Figure 2. Note that there are two comparators
in the section. One comparator has an internally generated
voltage reference called V1 going to one of its inputs. The
other comparator has an internally generated voltage refer-
ence called V2 going to one of its inputs. Both comparators
have a common input at their noninverting input coming from
the internal integrator. The internal integrator is used for
integrating the composite sync signal. This signal comes
from the input side of the composite sync buffer and are
positive going sync pulses. The capacitor to the integrator is
internal to the LM1881. The capacitor charge current is set
by the value of the external resistor RSET. The output of the
integrator is going to be at a low voltage during the normal
horizontal lines because the integrator has a very short time
to charge the capacitor, which is during the horizontal sync
period. The equalization pulses will keep the output voltage
of the integrator at about the same level, below the V1.
During the vertical sync period the narrow going positive
pulses shown in Figure 1 is called the serration pulse. The
wide negative portion of the vertical sync period is called the
vertical sync pulse. At the start of the vertical sync period,
The LM1881 also generates a default vertical sync pulse
when the vertical sync period is unusually long and has no
serration pulses. With a very long vertical sync time the
integrator has time to charge its internal capacitor above the
voltage level V2. Since there is no falling edge at the end of
a serration pulse to clock the “D” flip-flop, the only high signal
going to the OR gate is from the default comparator when
output of the integrator reaches V2. At this time the R/S
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