DS90LV048A
Parameter Measurement Information
(Continued)
10088805
C
L
includes load and test jig capacitance.
S
1
= V
CC
for t
PZL
and t
PLZ
measurements.
S
1
= GND for t
PZH
and t
PHZ
measurements.
FIGURE 3. Receiver TRI-STATE Delay Test Circuit
10088806
FIGURE 4. Receiver TRI-STATE Delay Waveforms
Typical Application
Balanced System
10088807
FIGURE 5. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-002), AN-808,
AN-977, AN-971, AN-916, AN-805, AN-903. The latest appli-
cations material is available on the web at:
www.national.com/lvds.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
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4
in
This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω (selected to match the media), and is
located as close to the receiver input pins as possible. The
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