DS90C365 Pin Description —
FPD Link Transmitter
Pin Name
I/O No.
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential data output.
TxIN
I
21
TxOUT+
O
O
I
3
3
1
1
1
1
1
TxOUT−
Negative LVDS differential data output.
TxCLKIN
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
R_FB
I
TxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
Power supply pins for TTL inputs.
VCC
I
I
I
I
I
I
3
4
1
2
1
3
GND
Ground pins for TTL inputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
TRANSMITTER INPUT CLOCK
Applications Information
The transmitter input clock must always be present when the
device is enabled (PWR DOWN = HIGH). If the clock is
stopped, the PWR DOWN pin must be used to disable the
PLL. The PWR DOWN pin must be held low until after the
input clock signal has been reapplied. This will ensure a
proper device reset and PLL lock to occur.
The DS90C385/DS90C365 are backward compatible with
the DS90C383/DS90C363, DS90C383A/DS90C363A and
the TSSOP versions are a pin-for-pin replacements. The
device (DS90C385/DS90C365) utilizes a different PLL archi-
tecture employing an internal 7X clock for enhanced pulse
position control.
POWER SEQUENCING AND POWERDOWN MODE
This device (DS90C385/DS90C365) also features reduced
variation of the TCCD parameter which is important for dual
pixel applications. (See AN-1084) TCCD variation has been
measured to be less than 500ps at 85MHz under normal
operating conditions.
Outputs of the transmitter remain in TRI-STATE until the
power supply reaches 2V. Clock and data outputs will begin
to toggle 10 ms after VCC has reached 3V and the Power-
down pin is above 1.5V. Either device may be placed into a
powerdown mode at any time by asserting the Powerdown
pin (active low). Total power dissipation for each device will
decrease to 5 µW (typical).
This device may also be used as a replacement for the
DS90CF583/563 (5V, 65MHz) and DS90CF581/561 (5V,
40MHz) FPD-Link Transmitters with certain considerations/
modifications:
The transmitter input clock may be applied prior to powering
up and enabling the transmitter. The transmitter input clock
may also be applied after power up; however, the use of the
PWR DOWN pin is required as described in the Transmitter
Input Clock section. Do not power up and enable (PWR
DOWN = HIGH) the transmitter without a valid clock signal
applied to the TxCLK IN pin.
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of the transmitter.
2. The DS90C385/DS90C365 transmitter input and control
inputs accept 3.3V LVTTL/LVCMOS levels. They are not
5V tolerant.
3. To implement a falling edge device for the DS90C385/
DS90C365, the R_FB pin may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
The FPD Link chipset is designed to protect itself from
accidental loss of power to either the transmitter or receiver.
If power to the transmit board is lost, the receiver clocks
(input and output) stop. The data outputs (RxOUT) retain the
states they were in when the clocks stopped. When the
receiver board loses power, the receiver inputs are con-
trolled by a failsafe bias circuitry. The LVDS inputs are
High-Z during initial power on and power off conditions.
Current is limited (5 mA per input) by the fixed current mode
drivers, thus avoiding the potential for latchup when power-
ing the device.
TRANSMITTER CLOCK JITTER CYCLE-TO-CYCLE
Figures 15 and 16 illustrate the timing of the input clock
relative to the input data. The input clock (TxCLKin) is inten-
tionally shifted to the left −3ns and +3ns to the right when
data (Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter
is repeated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-
to-cycle jitter at 2µs period.
RECEIVER FAILSAFE FEATURE
The FPD Link receivers have input failsafe bias circuitry to
guarantee a stable receiver output for floating or terminated
receiver inputs. Under these conditions receiver inputs will
be pulled to a HIGH state. This is the case if not all data
channels are required in the application. Leave the extra
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVC-
MOS and LVTTL levels. These pins are not 5V tolerant.
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