DS90C385/DS90C365
AC Timing Diagrams
(Continued)
10086828
FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter
DS90C385 MTD56 (TSSOP) Package Pin Description —
FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLKIN
R_FB
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
O
O
I
I
O
O
I
I
I
I
I
I
I
No.
28
4
4
1
1
1
1
1
3
4
1
2
1
3
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
11
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