1.3 Clock Interface
Signal Name
X1
I
Type
67
Pin #
Description
REFERENCE CLOCK INPUT 25 MHz:
This pin is the pri-
mary clock reference input for the DP83846A and must be
connected to a 25 MHz 0.005% (±50 ppm) clock source.
The DP83846A supports CMOS-level oscillator sources.
REFERENCE CLOCK OUTPUT 25 MHz:
This pin is the
primary clock reference output.
X2
O
66
1.4 Special Connections
Signal Name
RBIAS
RESERVED
I
I/O
Type
3
Pin #
Description
Bias Resistor Connection. A 9.31 kΩ
1%
resistor should be
connected from RBIAS to ANA_GND.
1, 5, 8, 20,
RESERVED:
These pins must be left unconnected.
21, 22, 47,
63, 68, 69,
70, 71, 74,
75, 77, 78,
80
1.5 LED Interface
Signal Name
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
LED_SPEED
Type
S, O
S, O
S, O
S, O
S, O
O
33
32
31
30
29
28
Pin #
Description
FULL DUPLEX LED STATUS:
Indicates Full-Duplex sta-
tus.
COLLISION LED STATUS:
Indicates Collision activity in
Half Duplex mode.
GOOD LINK LED STATUS:
Indicates Good Link Status for
10BASE-T and 100BASE-TX.
TRANSMIT LED STATUS:
Indicates transmit activity. LED
is on for activity, off for no activity.
RECEIVE LED STATUS:
Indicates receive activity. LED is
on for activity, off for no activity.
SPEED LED STATUS:
Indicates link speed; high for 100
Mb/s, low for 10 Mb/s.
7
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