Signal Name
RX_CLK
Type
O, PU
45
Pin #
Description
RECEIVE CLOCK:
Provides the 25 MHz recovered receive
clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T
nibble mode.
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_ER/PAUSE_EN
O, PU/PD 38, 39, 40,
RECEIVE DATA:
Nibble wide receive data (synchronous to
41
corresponding RX_CLK, 25 MHz for 100BASE-TX mode,
2.5 MHz for 10BASE-T nibble mode). Data is driven on the
falling edge of RX_CLK. RXD[2] has an internal pulldown re-
sistor. The remaining RXD pins have pullups.
S, O, PU
46
RECEIVE ERROR:
Asserted high to indicate that an invalid
symbol has been detected within a received packet in
100BASE-TX mode.
RECEIVE DATA VALID:
Asserted high to indicate that valid
data is present on the corresponding RXD[3:0] for nibble
mode. Data is driven on the falling edge of the correspond-
ing RX_CLK.
RX_DV
O
44
1.2 10 Mb/s and 100 Mb/s PMD Interface
Signal Name
TD+, TD-
O
Type
Pin #
16, 17
Description
Differential common driver transmit output. These differen-
tial outputs are configurable to either 10BASE-T or
100BASE-TX signaling.
The DP83846A will automatically configure the common
driver outputs for the proper signal type as a result of either
forced configuration or Auto-Negotiation.
RD-, RD+
I
10, 11
Differential receive input. These differential inputs can be
configured to accept either 100BASE-TX or 10BASE-T sig-
naling.
The DP83846A will automatically configure the receive in-
puts to accept the proper signal type as a result of either
forced configuration or Auto-Negotiation.
6
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