frequency. This register can be loaded from either flash
program memory or Boot ROM and must be maintained for
the entire duration of the operation. The MICROWIRE/PLUS
ISP routine that is resident in the boot ROM requires that this
Register be defined prior to any access to the Flash memory.
Refer to section Section 11.7 MICROWIRE/PLUS ISP for
more information on available ISP commands. On Reset, the
PGMTIM register is loaded with the value that corresponds
to 10 MHz frequency for CKI.
11.0 In-System Programming
(Continued)
11.3.4 ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the
width of the timing pulses for write and erase operations. The
value to be written into this register is dependent on the
frequency of CKI and is shown in Table 8. This register must
be written before any write or erase operation can take
place. It only needs to be loaded once, for each value of CKI
TABLE 8. PGMTIM Register Format
PGMTIM
Register Bit
CKI Frequency Range
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
6
0
5
0
4
3
0
2
0
1
0
0
1
0
0
25 kHz–33.3 kHz
37.5 kHz–50 kHz
50 kHz–66.67 kHz
62.5 kHz–83.3 kHz
75 kHz–100 kHz
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
100 kHz–133 kHz
112.5 kHz–150 kHz
150 kHz–200 kHz
200 kHz–266.67 kHz
225 kHz–300 kHz
300 kHz–400 kHz
375 kHz–500 kHz
500 kHz–666.67 kHz
600 kHz–800 kHz
800 kHz–1.067 MHz
1 MHz–1.33 MHz
1.125 MHz–1.5 MHz
1.5 MHz–2 MHz
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
0
1
1
1
1
2 MHz–2.67 MHz
2.625 MHz–3.5 MHz
3.5 MHz–4.67 MHz
4.5 MHz–6 MHz
1
0
1
0
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
6 MHz–8 MHz
1
1
1
1
0
1
1
7.5 MHz–10 MHz
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11.4 MANEUVERING BACK AND FORTH BETWEEN
FLASH MEMORY AND BOOT ROM
actually jump to the Boot ROM, the Key bit must be set. This
is done by writing the value shown in Table 9 to the Key
register. The Key is a 6 bit key and, if the key matches, the
KEY bit will be set for 8 instruction cycles. The JSRB instruc-
tion must be executed while the KEY bit is set. If the KEY
does not match, then the KEY bit will not be set and the
JSRB will jump to the specified location in the flash memory.
In emulation mode, if a breakpoint is encountered while the
KEY is set, the counter that counts the instruction cycles will
be frozen until the breakpoint condition is cleared. If an
interrupt occurs while the key is set, the Key will expire
before interrupt service is complete. It is recommended
that the software globally disable interrupts before set-
ting the key and re-enable interrupts on completion of
Boot ROM execution. The Key register is a memory
mapped register. Its format when writing is shown in Table 9.
When using ISP, at some point, it will be necessary to
maneuver between the flash program memory and the Boot
ROM, even when using customized ISP routines. This is
because it’s not possible to execute from the flash program
memory while it’s being programmed.
Two instructions are available to perform the jumping back
and forth: Jump to Boot (JSRB) and Return to Flash (RETF).
The JSRB instruction is used to jump from flash memory to
Boot ROM, and the RETF is used to return from the Boot
ROM back to the flash program memory. See Section 22.0
Instruction Set for specific details on the operation of these
instructions.
The JSRB instruction must be used in conjunction with the
Key register. This is to prevent jumping to the Boot ROM in
the event of run-away software. For the JSRB instruction to
25
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