normally. If, however, VCC drops below Vbor, an internal reset
is generated, and the Idle Timer is preset with 00Fx. The
device now waits until VCC is greater than Vbor and the
countdown starts over. The functional operation of the device
is guaranteed down to the Vbor level.
10.0 Functional Description
(Continued)
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
WATCHDOG service window of 64k T0 clock cycles. The
Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low error
output on pin G1. This error output will continue until
16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the
G1 output will go high.
One exception to the above is that the brownout circuit will
insert a delay of approximately 3 ms on power up or any time
the VCC drops below a voltage of about 1.8V. The device will
be held in Reset for the duration of this delay before the Idle
Timer starts counting the 240 to 256 tC. This delay starts as
soon as the VCC rises above the trigger voltage (approxi-
mately 1.8V). This behavior is shown in Figure 9.
In Case 1, VCC rises from 0V and the on-chip RESET is
undefined until the supply is greater than approximately
1.0V. At this time the brownout circuit becomes active and
holds the device in RESET. As the supply passes a level of
about 1.8V, a delay of about 3 ms (td) is started and the Idle
Timer is preset to a value between 00F0 and 00FF (hex).
Once VCC is greater than Vbor and td has expired, the Idle
Timer is allowed to count down (tid).
10.7.1 External Reset
Case 2 shows a subsequent dip in the supply voltage which
goes below the approximate 1.8V level. As VCC drops below
Vbor, the internal RESET signal is asserted. When VCC rises
back above the 1.8V level, td is started. Since the power
supply rise time is longer for this case, td has expired before
VCC rises above Vbor and tid starts immediately when VCC is
The RESET input, when pulled low, initializes the device.
The RESET pin must be held low for a minimum of one
instruction cycle to guarantee a valid reset.
RESET may also be used to cause an exit from the HALT
mode.
greater than Vbor
.
A recommended reset circuit for this device is shown in
Case 3 shows a dip in the supply where VCC drops below
Vbor, but not below 1.8V. On-chip RESET is asserted when
VCC goes below Vbor and tid starts as soon as the supply
Figure 8.
goes back above Vbor
.
The internal reset will not be turned off until the Idle Timer
underflows. The internal reset will perform the same func-
tions as external reset. The device is guaranteed to operate
at the specified frequency down to the specified brownout
voltage. After the underflow, the logic is designed such that
no additional internal resets occur as long as VCC remains
above the brownout voltage.
The device is relatively immune to short duration negative-
going VCC transients (glitches). It is essential that good
filtering of VCC be done to ensure that the brownout feature
works correctly. Power supply decoupling is vital even in
battery powered systems.
20006312
FIGURE 8. Reset Circuit Using External Reset
Refer to the device specifications for the actual Vbor voltage.
10.7.2 On-Chip Brownout Reset
Under no circumstances should the RESET pin be allowed
to float. If the external Reset feature is not being used, the
RESET pin should be connected directly to VCC. The RESET
input may also be connected to an external pull-up resistor
or to other external circuitry. The output of the brownout reset
detector will always preset the Idle Timer to a value between
00F0 and 00FF (240 to 256 tC). At this time, the internal reset
will be generated.
The device generates an internal reset as VCC rises. While
VCC is less than the specified brownout voltage (Vbor), the
device is held in the reset condition and the Idle Timer is
preset with 00Fx (240–256 tC). When VCC reaches a value
greater than Vbor, the Idle Timer starts counting down. Upon
underflow of the Idle Timer, the internal reset is released and
the device will start executing instructions. This internal reset
will perform the same functions as external reset. Once VCC
is above Vbor, and this initial Idle Timer time-out takes place,
instruction execution begins and the Idle Timer can be used
The contents of data registers and RAM are unknown fol-
lowing the on-chip reset.
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