AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of I HALT is done with device neither sourcing nor sinking current; with L, B, G0, and G2–G5
DD
programmed as low outputs and not driving a load; all inputs tied to V ; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode
CC
entered via setting bit 7 of the G Port data register.
>
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
V
and the pins will have sink current to V when
CC CC
>
biased at voltages
V
(the pins do not have source current when biased at a voltage below V ). These two pins will not latch up. The voltage at these pins must
C
C
C
C
<
be limited to (V + 7V). WARNING: Voltages in excess of (V
+ 7V) will cause damage to these pins. This warning excludes ESD transients.
CC
CC
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 7: Absolute Maximum Ratings should not be exceeded.
.
C
Note 8: Vcc must be valid and stable before G6 is raised to a high voltage.
A/D Converter Electrical Characteristics (−20˚C ≤ TA ≤ +85˚C)
(Single-ended mode only)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Max
Units
Bits
Resolution
DNL
10
1
VCC = 5V
LSB
LSB
LSB
LSB
V
INL
VCC = 5V
2.5
Offset Error
Gain Error
VCC = 5V
1.5
VCC = 5V
+0.5/-2.0
VCC
0.5
Input Voltage Range
4.5V ≤ VCC ≤ 5.5V
0
Analog Input Leakage Current
Analog Input Resistance (Note 9)
Analog Input Capacitance
µA
6k
Ω
7
pF
Conversion Clock Period
4.5V ≤ VCC ≤ 5.5V
0.8
30
µs
Conversion Time (Including S/H Time)
15
A/D
Conversion
Clock
Cycles
mA
Operating Current on AVCC
AVCC = 5.5V
0.2
0.6
Note 9: Resistance between the device input and the internal sample and hold capacitance.
www.national.com
12
NSC [ National Semiconductor ]
