ADC0816/ADC0817
Functional Description
Multiplexer:
The device contains a 16-channel single-ended
analog signal multiplexer. A particular input channel is se-
lected by using the address decoder.
Table 1
shows the input
states for the address line and the expansion control line to
select any channel. The address is latched into the decoder
on the low-to-high transition of the address latch enable
signal.
TABLE 1.
Selected
Analog Channel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
All Channels OFF
X=don’t care
Additional single-ended analog signals can be multiplexed to
the A/D converter by disabling all the multiplexer inputs using
the expansion control. The additional external signals are
connected to the comparator input and the device ground.
Additional signal conditioning (i.e., prescaling, sample and
hold, instrumentation amplification, etc.) may also be added
between the analog input signal and the comparator input.
CONVERTER CHARACTERISTICS
Address Line
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
Expansion
Control
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive
approximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach
Figure 1
was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause
oscillations that will be catastrophic for the system. Addition-
ally, the 256R network does not cause load variations on the
reference voltage.
The bottom resistor and the top resistor of the ladder net-
work in
Figure 1
are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transi-
tion occurs when the analog signal has reached +
1
⁄
2
LSB
and succeeding output transitions occur every 1 LSB later up
to full-scale.
DS005277-2
FIGURE 1. Resistor Ladder and Switch Tree
5
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