欢迎访问ic37.com |
会员登录 免费注册
发布采购

54ABT373CSJCX 参数 Datasheet PDF下载

54ABT373CSJCX图片预览
型号: 54ABT373CSJCX
PDF下载: 下载PDF文件 查看货源
内容描述: 八路透明锁存器具有三态输出 [Octal Transparent Latch with TRI-STATE Outputs]
分类和应用: 锁存器
文件页数/大小: 16 页 / 331 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
 浏览型号54ABT373CSJCX的Datasheet PDF文件第2页浏览型号54ABT373CSJCX的Datasheet PDF文件第3页浏览型号54ABT373CSJCX的Datasheet PDF文件第4页浏览型号54ABT373CSJCX的Datasheet PDF文件第5页浏览型号54ABT373CSJCX的Datasheet PDF文件第6页浏览型号54ABT373CSJCX的Datasheet PDF文件第7页浏览型号54ABT373CSJCX的Datasheet PDF文件第8页浏览型号54ABT373CSJCX的Datasheet PDF文件第9页  
54ABT 74ABT373 Octal Transparent Latch with TRI-STATE Outputs
September 1995
54ABT 74ABT373
Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH When LE is LOW the data that meets the setup
times is latched Data appears on the bus when the Output
Enable (OE) is LOW When OE is HIGH the bus output is in
the high impedance state
Y
Y
Y
Y
Y
Y
Features
Y
Y
Y
Y
TRI-STATE outputs for bus interfacing
Output sink capability of 64 mA source capability of
32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down
Nondestructive hot insertion capability
Standard Military Drawing (SMD) 5962-9321801
Commercial
74ABT373CSC (Note 1)
74ABT373CSJ (Note 1)
74ABT373CPC
Military
Package
Number
M20B
M20D
N20B
Package Description
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead Molded Thin Shrink Small Outline JEDEC
54ABT373J 883
74ABT373CMSA (Note 1)
54ABT373W 883
54ABT373E 883
74ABT373CMTC (Notes 1 2)
Note 2
Contact factory for package availability
J20A
MSA20
W20A
E20A
MTC20
Note 1
Devices also available in 13 reel Use suffix
e
SCX SJX MSAX and MTCX
Connection Diagrams
Pin Assignment
for DIP SOIC SSOP and Flatpak
Pin Assignment
for LCC
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
TL F 11547 – 2
TL F 11547–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 11547
RRD-B30M115 Printed in U S A