Functional Description
The ’ABT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
OE
L
L
L
H
H
H
L
X
Function Table
Inputs
LE
D
H
L
X
X
Outputs
O
H
L
O
0
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O
0
= Value stored from previous clock cycle
Logic Diagram
DS100219-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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