1.0 Architecture Overview
The Geode GXLV processor series represents the sixth
generation of x86-compatible 32-bit processors with sixth-
generation features. The decoupled load/store unit allows
reordering of load/store traffic to achieve higher perfor-
mance. Other features include single-cycle execution, sin-
gle-cycle instruction decode, 16 KB write-back cache, and
clock rates up to 266 MHz. These features are made pos-
sible by the use of advanced-process technologies and
pipelining.
The GXLV processor is divided into major functional
blocks (as shown in Figure 1-1):
•
•
•
•
•
•
Integer Unit
Floating Point Unit (FPU)
Write-Back Cache Unit
Memory Management Unit (MMU)
Internal Bus Interface Unit
Integrated Functions
Instructions are executed in the integer unit and in the
floating point unit. The cache unit stores the most recently
used data and instructions and provides fast access to
this information for the integer and floating point units.
The GXLV processor has low power consumption at all
clock frequencies. Where additional power savings are
required, designers can make use of Suspend Mode, Stop
Clock capability, and System Management Mode (SMM).
Write-Back
Cache Unit
Integer
FPU
MMU
Unit
C-Bus
Internal Bus Interface Unit
X-Bus
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
Integrated
Functions
PCI Bus
SDRAM Port
CS5530
(CRT/LCD TFT)
Figure 1-1. Internal Block Diagram
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