Signal Definitions (Continued)
Index Corner
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A
B
A
VCC3
AD25
VSS
VCC2
AD16
CBE2#
AD18 FRAME#
AD20 AD17 IRDY#
VCC2 VCC2 VSS DEVSEL# AD15
VCC3
TRDY# LOCK# CBE1#
VSS PAR VCC3
PERR# AD14 AD12
CBE0#
STOP# SERR#
VSS
AD11
AD13
AD10
AD8
VSS
AD5
VCC3
AD4
AD2
AD0
VCC2
VSS
TST0
TST2
IRQ13
MD0 MD32
VCC3
VSS
B
VSS
AD27
AD31 AD26
AD29 AD24
REQ0# REQ2# AD28
GNT0# TDI
CBE3#
AD23
AD22
AD21
AD19
AD9
AD7
AD6
AD3
SMI#
AD1
MD33
MD2
C
C
VCC3
VCC2
VCC2
VCC2
MD1
MD4
VSS
MD34
VCC3
D
D
AD30
INTR
TST1
TST3
MD3
MD5
MD6
MD35
E
E
VSS
VSS
VSS
VCC2
VSS
MD36
TDN
VSS
MD7
F
F
TDP
G
G
VSS CLKMODE2 VSS
GNT2# SUSPA#
MD37
H
H
MD38
J
J
TDO
VSS
TEST
VCC2
MD39
VCC2
VSS
K
K
REQ1# GNT1#
MD8
L
L
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
M
M
RESET SUSP#
MD40
MD9
N
N
VCC3
FPVSYN
SERIALP VSS
CKMD1 FPHSYN
TMS
VSS
VSS
MD41
P
P
TCK
MD10
MD11
MD44
MD14 MD13
MD15
VCC3
SYSCLK MD47
WEA# WEB# CASA#
DQM0 CASB#
DQM1 VSS
CS2#
CS0#
RASB# RASA#
MD42
MD43
MD12
Q
Q
NC
VSS
R
R
S
S
CKMD0 VID_VAL
PIX0
MD45
T
T
PIX1
PIX3
NC
PIX2
MD46
Geode™ GXm
Processor
U
U
VSS
PIX6
PIX8
VCC3
VCC3
VSS
VSS
VSS
V
V
VID_CLK
PIX5 PIX4
W
X
W
X
PIX9
320 SPGA - Top View
Y
Y
VSS
PIX7
VSS
DQM4
VCC3
Z
Z
NC
PIX10
DQM5
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
PIX11
PIX12 PIX13
VCC2 VCC2 VCC2
CRTHSYN DCLK
PIX14 VSS VCC2
PIX15 PIX16
VSS PIX17 VSS
CRTVSYN VDAT6
PCLK FLT# VDAT5
VRDY VSS VDAT0 SDCLK0 SDCLK2 SDCLKIN MD29
VCC2 VDAT4 VDAT2 SDCLK1 VCC2 RWCLK SDCLKOUT VSS
VDAT7 VDAT3 ENDIS SDCLK3 MD63 MD30 MD61
MD62 VCC3 MD28
VSS
VCC2
VCC2
VCC2
MA2
MA4
MA8
VSS
MA0
MA3
MA6
BA0
VCC2
VSS
MA1
VSS
VSS
MA5
MA10
VSS
VCC2
MD31
VSS
MD60
MD27
MD58
MD59 MD25
MD26
MD57
MD56
VCC3
MD24
MD54
VSS
MD22
MD55 MD21
MD23
MD53
MD52
VSS
VCC2
MD50
VCC2
VSS
BA1
MA9
MA7
MD20
MD16
MD49 VCC2
MD48 DQM7
MD17 VCC2 VSS
DQM3
DQM6
DQM2
CS1#
CS3#
VSS
MD19
CKEA
MA11
VCC3
MD51
MD18
MA12 VOLDET
VCC3 VSS
VSS
1
VCC2
3
VDAT1
5
VSS
7
VCC2
9
VSS
CKEB
VCC3
2
4
6
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Note: Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
For order information refer to Section A.1 “Order Information” on page 236.
Revision 3.1
19
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