Integrated Functions (Continued)
Table 4-35. Display Controller Palette and RAM Diagnostic Registers (Continued)
Bit
Name
Description
31:0
DISPLAY FIFO
Display FIFO Diagnostic Read or Write Data: Before this register is accessed, the DIAG bit in
DIAGNOSTIC
DATA
DC_GENERAL_CFG register should be set high and the DFLE bit should be set low. Since, each
FIFO entry is 64 bits, an even number of write operations should be performed. Each pair of write
operations will cause the FIFO write pointer to increment automatically. After all write operations
have been performed, a single read of don't care data should be performed to load data into the out-
put latch. Each subsequent read will contain the appropriate data which was previously written.
Each pair of read operations will cause the FIFO read pointer to increment automatically. A pause of
at least four core clocks should be allowed between subsequent read operations to allow adequate
time for the shift to take place.
GX_BASE+837Ch-837Fh
DC_CFIFO_DIAG Register (R/W)
Compressed Data FIFO Diagnostic Read or Write Data: Before this register is accessed, the
FIFO DIAGNOS- DIAG bit in DC_GENERAL_CFG register should be set high and the DFLE bit should be set low.
Default Value = xxxxxxxxh
31:0
COMPRESSED
TIC DATA
Also, the DIAG bit in DC_OUTPUT_CFG should be set high and the CFRW bit in
DC_OUTPUT_CFG should be set low. After each write, the FIFO write pointer will automatically
increment. After all write operations have been performed, the CFRW bit of DC_OUTPUT_CFG
should be set high to enable read addresses to the FIFO and a single read of don't care data should
be performed to load data into the output latch. Each subsequent read will contain the appropriate
data which was previously written. After each read, the FIFO read pointer will automatically incre-
ment.
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