Integrated Functions (Continued)
Table 4-32. Display Controller Timing Registers (Continued)
Bit
Name
Description
10:3
H_BLK_START
Horizontal Blank Start: This field represents the character clock count at which the horizontal
blanking signal becomes active minus 1. The field [10:0] may be programmed with the pixel count
minus 1, although bits [2:0] are ignored. The blank start position is programmable on 8-pixel bound-
aries only.
2:0
RSVD
Reserved: These bits are readable and writable but have no effect.
Note: A minimum of four character clocks is required for the horizontal blanking portion of a line in order for the timing generator to
function correctly.
GX_BASE+8338h-833Bh
DC_H_TIMING_3 Register (R/W)
Reserved: Set to 0.
Default Value = xxxxxxxxh
31:27
26:19
RSVD
H_SYNC_END
Horizontal Sync End: This field represents the character clock count at which the CRT horizontal
sync signal becomes inactive minus 1. The field [26:16] may be programmed with the pixel count
minus 1, although bits [18:16] are ignored. The sync end position is programmable on 8-pixel bound-
aries only.
18:16
15:11
10:3
RSVD
RSVD
Reserved: These bits are readable and writable but have no effect.
Reserved: Set to 0.
H_SYNC_START Horizontal Sync Start: This field represents the character clock count at which the CRT horizontal
sync signal becomes active minus 1. The field [10:0] may be programmed with the pixel count minus
1, although bits [2:0] are ignored. The sync start position is programmable on 8-pixel boundaries
only.
2:0
RSVD
Reserved: These bits are readable and writable but have no effect.
Note: This register should also be programmed appropriately for flat panel only display since the horizontal sync transition deter-
mines when to advance the vertical counter.
GX_BASE+833Ch-833Fh
C_FP_H_TIMING Register (R/W)
Reserved: Set to 0.
Default Value = xxxxxxxxh
31:27
26:16
RSVD
FP_H_SYNC
_END
Flat Panel Horizontal Sync End: This field represents the pixel count at which the flat panel hori-
zontal sync signal becomes inactive minus 1.
15:11
10:0
RSVD
Reserved: Set to 0.
FP_H_SYNC
_START
Flat Panel Horizontal Sync Start: This field represents the pixel count at which the flat panel hori-
zontal sync signal becomes active minus 1.
Note: All values are specified in pixels rather than character clocks to allow precise control over sync position. Note, however, that for
flat panels which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee
that the sync signal will meet proper setup and hold times.
GX_BASE+8340h-8343h
DC_V_TIMING_1 Register (R/W)
Reserved: Set to 0.
Default Value = xxxxxxxxh
31:27
26:16
RSVD
V_TOTAL
Vertical Total: This field represents the total number of lines for a given frame scan minus 1. Note
that the value is necessarily greater than the V_ACTIVE field because it includes border lines and
blanked lines. If the display is interlaced, the total number of lines must be odd, so this value should
be an even number.
15:11
10:0
RSVD
Reserved: Set to 0.
V_ACTIVE
Vertical Active: This field represents the total number of lines for the displayed portion of a frame
scan minus 1. Note that for flat panels, if this value is less than the panel active vertical resolution
(V_PANEL), the parameters V_BLANK_START, V_BLANK_END, V_SYNC_START, and
V_SYNC_END should be reduced by the following value (V_ADJUST) to achieve vertical centering:
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value should be an odd
number.
Note: All values are specified in lines.
GX_BASE+8344h-8347h
DC_V_TIMING_2 Register (R/W)
Reserved: Set to 0.
Default Value = xxxxxxxxh
31:27
26:16
RSVD
V_BLANK_END
Vertical Blank End: This field represents the line at which the vertical blanking signal becomes
inactive minus 1. If the display is interlaced, no border is supported, so this value should be identical
to V_TOTAL.
15:11
RSVD
Reserved: Set to 0.
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