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30151-33 参数 Datasheet PDF下载

30151-33图片预览
型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Table 2-1. Pin Type Definitions  
Mnemonic Definition  
Standard input pin.  
2.0 Signal Definitions  
This section describes the external interface of the Geode  
GXm processor. Figure 2-1 shows the signals organized  
by their functional interface groups (internal test and elec-  
trical pins are not shown).  
I
I/O  
O
Bidirectional pin.  
Totem-pole output.  
2.1 PIN ASSIGNMENTS  
The tables in this section use several common abbrevia-  
tions. Table 2-1 lists the mnemonics and their meanings.  
OD  
Open-drain output structure that allows  
multiple devices to share the pin in a  
wired-OR configuration  
PU  
Pull-up resistor  
Figure 2-2 on page 14 shows the pin assignment for the  
352 BGA with Tables 2-2 and 2-3 listing the pin assign-  
ments sorted by pin number and alphabetically by signal  
name, respectively.  
PD  
Pull-down resistor  
s/t/s  
Sustained tri-state, an active-low tri-state  
signal owned and driven by one and only  
one agent at a time. The agent that  
Figure 2-3 on page 19 shows the pin assignment for the  
320 SPGA with Tables 2-4 and 2-5 listing the pin assign-  
ments sorted by pin number and alphabetically by signal  
name, respectively.  
drives an s/t/s pin low must drive it high  
for at least one clock before letting it float.  
A new agent cannot start driving an s/t/s  
signal any sooner than one clock after  
the previous owner lets it float. A pull-up  
resistor is required to sustain the inactive  
state until another agent drives it, and  
must be provided by the central resource.  
In Section 2.2 “Signal Descriptions” starting on Page 24 a  
description of each signal is provided within its associated  
functional group.  
Following the signal descriptions, information regarding  
subsystem signal connections and split power planes and  
decoupling is provided.  
VCC (PWR) Power pin.  
VSS (GND) Ground pin  
#
The "#" symbol at the end of a signal  
name indicates that the active, or  
.
asserted state occurs when the signal is  
at a low voltage level. When "#" is not  
present after the signal name, the signal  
is asserted when at a high voltage level.  
SYSCLK  
CLKMODE[2:0]  
RESET  
MD[63:0]  
MA[12:0]  
BA[1:0]  
System  
Interface  
Signals  
INTR  
IRQ13  
SMI#  
RASA#, RASB#  
CASA#, CASB#  
CS[3:0]#  
WEA#, WEB#  
DQM[7:0]  
CKEA, CKEB  
SDCLK[3:0]  
SDCLK_IN  
SDCLK_OUT  
Memory  
Controller  
Interface  
Signals  
SUSP#  
SUSPA#  
SERIALP  
Geode™ GXm  
Processor  
AD[31:0]  
C/BE[3:0]#  
PAR  
PCLK  
FRAME#  
IRDY#  
VID_CLK  
DCLK  
TRDY#  
STOP#  
LOCK#  
DEVSEL#  
PERR#  
CRT_HSYNC  
CRT_VSYNC  
FP_HSYNC  
FP_VSYNC  
ENA_DISP  
VID_RDY  
PCI  
Interface  
Signals  
Video  
Interface  
Signals  
SERR#  
REQ[2:0]#  
GNT[2:0]#  
VID_VAL  
VID_DATA[7:0]  
PIXEL[17:0]  
Figure 2-1. Functional Block Diagram  
Revision 3.1  
13  
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