Instruction Set (Continued)
Table 9-27. Processor Core Instruction Set Summary
Real
Mode
Prot’d Real Prot’d
Mode Mode Mode
Flags
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Clock Count
(Reg/Cache Hit)
Instruction
Opcode
Notes
AAA ASCII Adjust AL after Add
AAD ASCII Adjust AX before Divide
AAM ASCII Adjust AX after Multiply
AAS ASCII Adjust AL after Subtract
ADC Add with Carry
37
u
u
u
u
-
-
-
-
-
-
-
-
u
x
x
u
u
x
x
u
x
u
u
x
u
x
x
u
x
u
u
x
3
7
3
7
D5 0A
D4 0A
3F
-
-
19
3
19
3
-
-
Register to Register
1 [00dw] [11 reg r/m]
1 [000w] [mod reg r/m]
1 [001w] [mod reg r/m]
8 [00sw] [mod 010 r/m]###
1 [010w] ###
x
x
0
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
-
x
x
x
x
x
x
u
-
x
x
x
-
x
x
0
-
1
1
1
1
1
1
1
1
1
1
b
b
b
a
h
h
h
h
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
ADD Integer Add
Register to Register
0 [00dw] [11 reg r/m]
0 [000w] [mod reg r/m]
0 [001w] [mod reg r/m]
8 [00sw] [mod 000 r/m]###
0 [010w] ###
1
1
1
1
1
1
1
1
1
1
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
AND Boolean AND
Register to Register
2 [00dw] [11 reg r/m]
2 [000w] [mod reg r/m]
2 [001w] [mod reg r/m]
8 [00sw] [mod 100 r/m]###
2 [010w] ###
1
1
1
1
1
1
1
1
1
1
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
ARPL Adjust Requested Privilege Level
From Register/Memory
63 [mod reg r/m]
9
2
2
BB0_Reset Set BLT Buffer 0 Pointer to the Base 0F 3A
BB1_Reset Set BLT Buffer 1 Pointer to the Base 0F 3B
BOUND Check Array Boundaries
2
2
If Out of Range (Int 5)
If In Range
62 [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8+INT 8+INT
b, e g,h,j,k,r
7
7
BSF Scan Bit Forward
Register, Register/Memory
BSR Scan Bit Reverse
Register, Register/Memory
BSWAP Byte Swap
0F BC [mod reg r/m]
x
4/9+n
4/9+n
b
b
h
h
0F BD [mod reg r/m]
0F C[1 reg]
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
4/11+n 4/11+n
6
6
BT Test Bit
Register/Memory, Immediate
Register/Memory, Register
BTC Test Bit and Complement
Register/Memory, Immediate
Register/Memory, Register
BTR Test Bit and Reset
Register/Memory, Immediate
Register/Memory, Register
BTS Test Bit and Set
0F BA [mod 100 r/m]#
0F A3 [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
1
1
b
b
b
b
h
h
h
h
1/7
1/7
0F BA [mod 111 r/m]#
0F BB [mod reg r/m]
2
2
2/8
2/8
0F BA [mod 110 r/m]#
0F B3 [mod reg r/m
2
2
2/8
2/8
Register/Memory
0F BA [mod 101 r/m]
0F AB [mod reg r/m]
2
2
Register (short form)
2/8
2/8
Revision 3.1
213
www.national.com
NSC [ National Semiconductor ]
