Instruction Set (Continued)
Table 9-19. EDX CPUID Data
9.2.1.3 CPUID Instruction with EAX = 00000002h
Standard function 02h (EAX = 02h) of the CPUID instruc-
tion returns information that is specific to the National
Semiconductor family of processors. Information about
the TLB is returned in EAX as shown in Table 9-20. Infor-
mation about the L1 cache is returned in EDX.
Returned when EAX = 1
Returned
CR4
Bit
EDX
EDX[0]
Contents*
Feature Flag
FPU On-Chip
1
0
0
0
1
1
-
-
EDX[1]
EDX[2]
EDX[3]
EDX[4]
EDX[5]
Virtual Mode Extension
Debug Extensions
-
Table 9-20. Standard CPUID with
EAX = 00000002h
Page Size Extensions
Time Stamp Counter
-
2
-
Returned
RDMSR / WRMSR
Instructions
Register
Contents
Description
EAX
xx xx 70 xxh TLB is 32 Entry, 4-way set asso-
ciative, and has 4 KByte Pages
EDX[6]
0
Physical Address
Extensions
-
EAX
xx xx xx 01h The CPUID instruction needs to
be executed only once with an
input value of 02h to retrieve
complete information about the
cache and TLB
EDX[7]
EDX[8]
EDX[9]
EDX[10]
EDX[11]
0
1
0
0
0
Machine Check Exception
CMPXCHG8B Instruction
On-Chip APIC Hardware
Reserved
-
-
-
-
-
EBX
ECX
EDX
Reserved
Reserved
SYSENTER / SYSEXIT
Instructions
EDX[12]
0
Memory Type Range
Registers
-
xx xx xx 80h L1 cache is 16 KBytes, 4-way set
associated, and has 16 bytes per
line.
EDX[13]
EDX[14]
0
0
Page Global Enable
-
-
Machine Check
Architecture
EDX[15]
1
Conditional Move
Instructions
-
EDX[16]
EDX[22:17]
EDX[23]
EDX[24]
0
0
1
0
Page Attribute Table
Reserved
-
-
-
-
MMX Instructions
Fast FPU Save and
Restore
EDX[31:25]
0
Reserved
-
Note: *0 = Not supported
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