Instruction Set (Continued)
9.1 GENERAL INSTRUCTION SET FORMAT
Depending on the instruction, the GXm processor core
instructions follow the general instruction format shown in
Table 9-1.
diate data. An instruction can be as short as one byte and
as long as 15 bytes. If there are more than 15 bytes in the
instruction, a general protection fault (error code 0) is gen-
erated.
These instructions vary in length and can start at any byte
address. An instruction consists of one or more bytes that
can include prefix bytes, at least one opcode byte, a mod
r/m byte, an s-i-b byte, address displacement, and imme-
The fields in the general instruction format at the byte
level are summarized in Table 9-2 and detailed in the fol-
lowing subsections.
Table 9-1. General Instruction Set Format
Register and Address Mode Specifier
mod r/m Byte
s-i-b Byte
Address
Displacement
Immediate
Data
Prefix (optional)
Opcode
mod
7:6
reg
r/m
ss
index
base
0 or More Bytes
1 or 2 Bytes
5:3
2:0
7:6
5:3
2:0
0, 8, 16, or 32 Bits 0, 8, 16, or 32 Bits
Table 9-2. Instruction Fields
Field Name
Description
Prefix (optional)
Prefix Field(s): One or more optional fields that are used to specify segment register override, address
and operand size, repeat elements in string instruction, LOCK# assertion.
Opcode
Opcode Field: Identifies instruction operation.
mod
Address Mode Specifier: Used with r/m field to select addressing mode.
General Register Specifier: Uses reg, sreg3 or sreg2 encoding depending on opcode field.
Address Mode Specifier: Used with mod field to select addressing mode.
Scale factor: Determines scaled-index address mode.
reg
r/m
ss
index
Index: Determines general register to be used as index register.
Base: Determines general register to be used as base register.
Displacement: Determines address displacement.
base
Address Displacement
Immediate Data
Immediate Data: Immediate-data operand used by instruction.
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