Integrated Functions (Continued)
4.3.2 Memory Organizations
The memory controller supports JEDEC standard synchronous DRAMs in 16 Mb and 64 Mb configurations. Supported
configurations are shown in Table 4-12.
Table 4-12. Synchronous DRAM Configurations
Row
Bank
Total # of
Depth
Organization
Address
Column Address
Address
Address bits
1
2
1 Mx16
2 Mx8
A10-A0
A10-A0
A10-A0
A10-A0
A11-A0
A12-A0
A10-A0
A11-A0
A12-A0
A10-A0
A11-A0
A12-A0
A11-A0
A12-A0
A11-A0
A12-A0
A12-A0
A11-A0
A12-A0
A12-A0
A7-A0
A8-A0
A7-A0
A8-A0
A6-A0
A6-A0
A9-A0
A7-A0
A7-A0
A9-A0
A8-A0
A8-A0
A8-A0
A7-A0
A9-A0
A9-A0
A8-A0
A9-A0
A9-A0
A9-A0,A11
BA0
BA0
20
21
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
25
26
2 Mx32
2 Mx32
2 Mx32
2 Mx32
4 Mx4
BA1-BA0
BA0
BA1-BA0
BA0
4
8
BA0
4 Mx16
4 Mx16
4 Mx16
8 Mx8
BA1-BA0
BA0
BA0
BA1-BA0
BA0
8 Mx8
8 Mx32
8 Mx32
16 Mx4
16 Mx4
16 Mx16
16 Mx16
32 Mx8
64 Mx4
BA1-BA0
BA1-BA0
BA1-BA0
BA0
16
BA1-BA0
BA1-BA0
BA1-BA0
BA1-BA0
32
64
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