Integrated Functions (Continued)
4.2.5 Internal Bus Interface Unit Registers
The Internal Bus Interface Unit maps 100h locations start-
ing at GX_BASE+8000h. Refer to Section 4.1.2 “Control
Registers” on page 94 for instructions on accessing these
registers.
Table 4-9 summarizes the four 32-bit registers contained
in the Internal Bus Interface Unit and Table 4-10 gives the
register/bit formats.
Table 4-9. Internal Bus Interface Unit Register Summary
GX_BASE+
Memory Offset
Default
Value
Type
Name/Function
BC_DRAM_TOP
8000h-8003h
R/W
3FFFFFFFh
Top of DRAM: Contains the highest available address of system memory not
including the memory that is set aside for graphics memory, which corresponds to
1 GByte of memory. The largest possible value for the register is 3FFFFFFFh.
8004h-8007h
R/W
BC_XMAP_1
00000000h
Memory X-Bus Map Register 1 (A and B Region Control: Contains the region
control of the A and B regions and the SMI controls required for VGA emulation.
PCI access to internal registers and the A20M function are also controlled by this
register.
8008h-800Bh
800Ch-800Fh
R/W
R/W
BC_XMAP_2
00000000h
00000000h
Memory X-Bus Map Register 2 (C and D Region Control): Contains region con-
trol fields for eight regions in the address range C0h through DCh.
BC_XMAP_3
Memory X-Bus Map Register 3 (E and F Region Control): Contains the region
control fields for memory regions in the address range E0h through FCh.
Table 4-10. Internal Bus Interface Unit Registers
Bit
Name
Description
GX_BASE+8000h-8003h
BC_DRAM_TOP Register (R/W)
Default Value = 3FFFFFFFh
Default Value = 00000000h
31:30
29:17
RSVD
Reserved: Set to 0.
TOP OF
DRAM
Top of DRAM: Maximum value is FFFh.
16:0
1FFFF
Granularity: Must be set to 1FFFFh (128 KB).
BC_XMAP_1 Register (R/W)
Reserved: Set to 0.
GX_BASE+8004h-8007h
31:29
28
RSVD
GEB8
Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h-BFFFFh be
directed to the graphics pipeline: 0 = Disable; 1 = Enable.
(Used for VGA emulation.)
27:24
B8
B8 Region: Region control field for address range B8000h-BFFFFh.
Note: Refer to Table 4-11 for decode.
Reserved: Set to 0.
23
22
RSVD
PRAE
PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus:
0 = Disable; 1 = Enable.
21
20
A20M
GEB0
Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses:
0 = Disable; 1 = Enable.
Graphics Enable for B0 Region: Allow memory R/W operations for address range B0000h-B7FFFh be
directed to the graphics pipeline: 0 = Disable; 1 = Enable.
(Used for VGA emulation.)
19:16
15
B0
B0 Region: Region control field for address range B0000h-B7FFFh.
Note: Refer to Table 4-11 for decode.
SMID
SMIC
SMIB
SMID: All I/O accesses for address range 3D0h-3DFh generate an SMI: 0 = Disable; 1 = Enable.
(Used for VGA virtualization.)
14
SMIC: All I/O accesses for address range 3C0h-3CFh generate an SMI: 0 = Disable; 1 = Enable.
(Used for VGA virtualization.)
13
SMIB: All I/O accesses for address range 3B0h-3BFh generate an SMI: 0 = Disable; 1 = Enable
(Used for VGA virtualization.)
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