Processor Programming (Continued)
3.7.2 Segment Mechanism in Protective Mode
The segment mechanism in protective mode is more com-
plex. Basically as in Real and Virtual 8086 modes the off-
set address is added to the segment base address to
produce a linear address (Figure 3-5). However, the cal-
culation of the segment base address is based on the
contents of descriptor tables.
divided in to three fields: the RPL, TI and INDEX fields as
shown in Figure 3-6.
The segments are assigned permission levels to prevent
application program errors from disrupting operating pro-
grams. The Requested Privilege Level (RPL) determines
the Effective Privilege Level of an instruction. RPL = 0 indi-
cates the most privileged level, and RPL = 3 indicates the
least privileged level. Refer to Section 3.13 “Protection” on
page 86.
Again, if paging is enabled the linear address is further
processed by the paging mechanism.
Descriptor tables hold descriptors that allow management
of segments and tables in address space while in protec-
tive mode. The Table Indicator Bit (TI) in the selector
selects either the General Descriptor Table (GDT) or one
Local Descriptor Tables (LDT) tables. If TI = 0, GDT is
selected; if TI =1, LDT is selected. The 13-bit INDEX field
in the segment selector is used to index a GDT or LDT
table.
A more detailed look at the segment mechanisms for real,
virtual 8086 and protective modes is illustrated in Figure
3-6. In protective mode, the segment selector is cached.
This is illustrated in Figure 3-7 on page 65.
3.7.2.1 Segment Selectors
The segment registers are used to store segment selec-
tors. In protective mode, the segment selectors are
32
Offset Address
Offset Mechanism
Linear
Address
Physical
Memory
Address
32
Optional
Paging Mechanism
32
Segment Base
Address
32
Selector Mechanism
Figure 3-5. Protected Mode Address Calculation
Revision 3.1
63
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