Processor Programming (Continued)
3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS
The mapping of address space into a sequence of mem-
ory locations (often cached) is performed by the offset,
segment and paging mechanisms.
Nine valid combinations of the base, index, scale factor
and displacement can be used with the CPU instruction
set. These combinations are listed in Table 3-19 on page
61. The base and index both refer to contents of a register
as indicated by [Base] and [Index].
In general, the offset, segment and paging mechanisms
work in tandem as shown below:
In real mode operation, the CPU only addresses the low-
est 1 MB of memory and the offset contains 16-bits. In
protective mode the offset contains 32 bits. Initialization
and transition to protective mode is described in Section
3.13.4 “Initialization and Transition to Protected Mode” on
page 87.
instruction offset offset mechanism offset address
offset address
segment mechanism linear address
linear address paging mechanism physical page.
As will be explained, the actual operations depend on sev-
eral factors such as the current operating mode and if
paging is enabled. Note: the paging mechanism uses part
of the linear address as an offset on the physical page.
Index
3.6 OFFSET MECHANISM
In all operating modes, the offset mechanism computes
an offset (effective) address by adding together up to
three values: a base, an index and a displacement. The
base, if present, is the value in one of eight general regis-
ters at the time of the execution of the instruction. The
index, like the base, is a value that is contained in one of
the general registers (except the ESP register) when the
instruction is executed. The index differs from the base in
that the index is first multiplied by a scale factor of 1, 2, 4
or 8 before the summation is made. The third component
added to the memory address calculation is the displace-
ment that is a value supplied as part of the instruction.
Figure 3-3 illustrates the calculation of the offset address.
Base
Displacement
Scaling
x1, x2, x4, x8
+
Offset Address
(Effective Address)
Figure 3-3. Offset Address Calculation
Table 3-19. Memory Addressing Modes
Scale
Factor
(SF)
Displacement
Offset Address (OA)
Calculation
Addressing Mode
Direct
Base
Index
(DP)
x
OA = DP
Register Indirect
Based
x
x
OA = [BASE]
x
x
x
OA = [BASE] + DP
Index
x
x
x
x
x
OA = [INDEX] + DP
Scaled Index
Based Index
Based Scaled Index
x
x
OA = ([INDEX] * SF) + DP
OA = [BASE] + [INDEX]
OA = [BASE] + ([INDEX] * SF)
OA = [BASE] + [INDEX] + DP
x
x
x
Based Index with
Displacement
x
x
Based Scaled Index with
Displacement
x
x
x
OA = [BASE] + ([INDEX] * SF) + DP
Revision 3.1
61
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