Power Management (Continued)
selected by setting bit 0 in the PM Clock Stop Control
Register. If you are using DRAMs without self refresh, you
must supply a 32 kHz clock to the CLK32KHZ bit to keep
the refresh circuitry active when using the lower-power
Suspend mode.
power mode turns off all internal clocks generated from
SYSCLK. This mode is selected by setting bit 0 in the PM
Clock Stop Control Register. If the bit is set and DRAMS
without self-refresh are used, a 32 KHz clock must be
supplied to the CLK32KHZ input to keep the refresh circuit
active.
While also in 3-Volt Suspend Mode, the CS5530 contin-
ues to decrement all of its device timers, and it responds
to external SMI interrupts using the 32 kHz clock input
(CLK32KHz) pin. Any SMI event, timer or pin, causes the
CS5530 to deassert the SUSP_3V pin, starting the sys-
tem clocks. The CS5530 holds SUSP# active for a pre-
programmed period that varies from 0 to 16 ms, which
allows the clocks to settle. After this period expires, the
CS5530 deasserts SUSP#. SMI# is held active for the
entire period, so that the GXm processor status registers
are updated.
The GXm processor enters the Suspend mode in
response to SUSP# input assertion only when certain
conditions are met. First, the USE_SUSP bit must be set
in CCR2 (Index C2h[7]). In addition, execution of the cur-
rent instructions and any pending decoded instructions
and associated bus cycles must be completed. SUSP# is
sampled on the rising edge of SYSCLK, and must meet
specified setup and hold times to be recognized at a par-
ticular SYSCLK edge.
When all conditions are met, the SUSPA# output is
asserted. The time from assertion of SUSP# to the activa-
tion of SUSPA# depends on which instructions were
decoded prior to assertion of SUSP#. Normally, once
SUSP# has been sampled inactive the SUSPA# output
will be deactivated within two clocks. However, the deacti-
vation of SUSPA# may be delayed until the end of an
active refresh cycle.
The SUSP_3V pin can be active either high or low. The
pin is an input during POR, and is sampled to determine
its inactive state. This allows a designer to match the
active state of SUSP_3V to the inactive state for a clock
driver output enable with a pull-up or pull-down resistor.
6.5 SUSPEND MODE AND BUS CYCLES
The following subsections describe the bus cycles when
the Suspend mode is implemented.
If the CPU is already in a Suspend mode initiated by
SUSP#, one occurrence of NMI, INTR and SMI# is stored
for execution after Suspend mode is exited. The CPU also
allows PCI accesses during a SUSP#-initiated Suspend
mode (see Figure 6-1). If the CPU is in the middle of a
PCI access when SUSP# is asserted, the assertion of
SUSPA# will be delayed until the PCI access is com-
pleted.
6.5.1 Initiating Suspend with SUSP#
The GXm processor has two low-power Suspend modes.
The mode is selected by bit 0 in the PM Clock Stop Con-
trol Register. One mode (bit 0 cleared) turns off the inter-
nal clocks to everything but the internal Display and
Memory Controllers, keeping the display active. A lower-
SYSCLK
SUSP#
SUSPA#
Figure 6-1. SUSP#-Initiated Suspend Mode
Revision 3.1
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