Virtual Subsystem Architecture (Continued)
Table 5-5. Virtual VGA Registers
Bit
Name
Description
GX_BASE+8210h-8213h
GP_VGA_BASE (R/W)
Default Value = xxxxxxxxh
31:14
13:8
RSVD
Reserved: Set to 0.
VGA_BASE
(RO)
Base Address (Read Only): The VGA base address is added to the graphics memory base to
specify where VGA memory starts. The VGA base address provides longword address bits 19:14
when mapping VGA accesses into graphics memory. This allows the VGA base address to start on
any 64 KB boundary within the 4 MB of graphics memory.
7:6
5:0
RSVD
Reserved: Set to 0.
VGA_BASE
(WO)
Base Address (Write Only): The VGA base address is added to the graphics memory base to
specify where VGA memory starts. The VGA base address provides longword address bits 19:14
when mapping VGA accesses into graphics memory. This allows the VGA base address to start on
any 64 KB boundary within the 4 MB of graphics memory.
GX_BASE+8214h-8217h
31:0 LATCH
GP_VGA_LATCH Register (R/W)
Default Value = xxxxxxxxh
Display Latch: Specifies the value in the VGA display latch. VGA read operations cause VGA
frame-buffer data to be latched in the display latch. VGA write operations can use the display latch
as a source of data for VGA frame-buffer write operations.
GX_BASE+8140h-8143h
GP_VGA_WRITE Register (R/W)
Reserved: Set to 0.
Default Value = xxxxxxxxh
31:28
27:24
RSVD
MAP_MASK
Map Mask: Enables planes 3 through 0 for writing. Combined with chain control to determine the
final enables.
23:21
20
RSVD
W3
Reserved: Set to 0.
Write Mode 3: Selects write mode 3 by using the bit mask with the rotated data.
Write Mode 2: Selects write mode 2 by controlling set/reset.
Rotate Count: Controls the eight bit rotator.
19
W2
18:16
15:12
11:8
7:0
RC
SRE
Set/Reset Enable: Enables the set/reset value for each plane.
Set/Reset: Selects 1 or 0 for each plane if enabled.
Bit Mask: Selects data from the data latches (last read data).
SR
BIT_MASK
GX_BASE+8144h-8147h
GP_VGA_READ Register (R/W)
Reserved: Set to 0.
Default Value = 00000000h
31:18
17:16
15
RSVD
RMS
F15
Read Map Select: Selects which plane to read in read mode 0 (Chain 2 and Chain 4 inactive).
Force Address Bit 15: Forces address bit 15 to 0.
14
PC4
Packed Chain 4:— Provides 64 KB of packed pixel addressing when used with Chain 4 mode. This
bit causes the VGA addresses to be shifted right by 2 bits.
13
12
11
10
9
C4
PB
Chain 4 Mode: Selects Chain 4 mode for both read operations and write operations.
Page Bit: Becomes LSB of address if COE is set high.
COE
W2
Chain Odd/Even: Selects PB rather than A0 for least-significant VGA address bit.
Write Chain 2 Mode: Selects Chain 2 mode for write operations.
R2
Read Chain 2 Mode: Selects Chain 2 mode for read operations.
8
RM
CCM
CC
Read Mode: Selects between read mode 0 (normal) and read mode 1 (color compare).
Color Compare Mask: Selects planes to include in the color comparison (read mode 1).
Color Compare: Specifies value of each plane for color comparison (read mode 1).
7:4
3:0
Revision 3.1
173
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