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30134-23 参数 Datasheet PDF下载

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型号: 30134-23
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内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Instruction Set (Continued)  
8.6 EXTENDED MMX INSTRUCTION SET  
National Semiconductor has added instructions to its  
implementation of the Intel MMX architecture in order to  
facilitate writing of multimedia applications. In general,  
these instructions allow more efficient implementation of  
multimedia algorithms, or more precision in computation  
than can be achieved using the basic set of MMX instruc-  
tions. All of the added instructions follow the SIMD (single  
instruction, multiple data) format. Many of the instructions  
add flexibility to the MMX architecture by allowing both  
source operands of an instruction to be preserved, while  
the result goes to a separate register that is derived from  
the input.  
Table 8-32. Extend MMX Instruction Set  
Table Legend  
Abbreviation  
Description  
<----  
Result written.  
[11 mm reg]  
mm  
Binary or binary groups of digits.  
One of eight 64-bit MMX registers.  
A general purpose register.  
reg  
<--sat--  
If required, the resultant data is saturated  
to remain in the associated data range.  
<--move--  
[byte]  
Source data is moved to result location.  
Table 8-33 summarizes the Extended MMX Instructions.  
The abbreviations used in the table are listed in Table 8-  
32.  
Eight 8-bit BYTEs are processed in paral-  
lel.  
[word]  
Four 16-bit WORDs are processed in par-  
allel.  
Configuration control register CCR7(0) at Index EBh (see  
Table 3-11 on page 53) must be set to allow the execution  
of the Extended MMX instructions.  
[dword]  
Two 32-bit DWORDs are processed in par-  
allel.  
[qword]  
One 64-bit QWORD is processed.  
[sign xxx]  
The BYTE, WORD, DWORD or QWORD  
most significant bit is a sign bit.  
mm1, mm2  
mod r/m  
MMX Register 1, MMX Register 2.  
Mod and r/m byte encoding (Table 8-15 on  
page 217).  
pack  
Source data is truncated or saturated to  
next smaller data size, then concatenated.  
packdw  
Pack two DWORDs from source and two  
DWORDs from destination into QWORDs  
in destination register.  
packwb  
Pack QWORDs from source and QWORDs  
from destination into eight BYTEs in desti-  
nation register.  
www.national.com  
244  
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