Instruction Set (Continued)
Table 8-31. MMX Instruction Set Summary (Continued)
MMX Instructions
Opcode
Operation and Clock Count (Latency/Throughput)
PSLLW Packed Shift Left Logical Word
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FF1 [11 mm1 mm2] MMX reg 1 [word] <--shift left, shifting in zeroes by MMX reg 2 [word]--
0FF1 [mod mm r/m] MMX reg [word] <--shift left, shifting in zeroes by memory[word]--
0F71 [11 110mm] # MMX reg [word] <--shift left, shifting in zeroes by [im byte]--
1/1
1/1
1/1
MMX Register by Immediate
PSRAD Packed Shift Right Arithmetic Dword
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FE2 [11 mm1 mm2] MMX reg 1 [dword] <--arith shift right, shifting in zeroes by MMX reg 2 [dword--] 1/1
0FE2 [mod mm r/m] MMX reg [dword] <--arith shift right, shifting in zeroes by memory[dword]--
0F72 [11 100 mm] # MMX reg [dword] <--arith shift right, shifting in zeroes by [im byte]--
1/1
1/1
MMX Register by Immediate
PSRAW Packed Shift Right Arithmetic Word
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FE1 [11 mm1 mm2] MMX reg 1 [word] <--arith shift right, shifting in zeroes by MMX reg 2 [word]--
0FE1 [mod mm r/m] MMX reg [word] <--arith shift right, shifting in zeroes by memory[word--]
0F71 [11 100 mm] # MMX reg [word] <--arith shift right, shifting in zeroes by [im byte]--
1/1
1/1
1/1
MMX Register by Immediate
PSRLD Packed Shift Right Logical Dword
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FD2 [11 mm1 mm2] MMX reg 1 [dword] <--shift right, shifting in zeroes by MMX reg 2 [dword]--
0FD2 [mod mm r/m] MMX reg [dword] <--shift right, shifting in zeroes by memory[dword]--
0F72 [11 010 mm] # MMX reg [dword] <--shift right, shifting in zeroes by [im byte]--
1/1
1/1
1/1
MMX Register by Immediate
PSRLQ Packed Shift Right Logical Qword
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FD3 [11 mm1 mm2] MMX reg 1 [qword] <--shift right, shifting in zeroes by MMX reg 2 [qword]
0FD3 [mod mm r/m] MMX reg [qword] <--shift right, shifting in zeroes by memory[qword]
0F73 [11 010 mm] # MMX reg [qword] <--shift right, shifting in zeroes by [im byte]
1/1
1/1
1/1
MMX Register by Immediate
PSRLW Packed Shift Right Logical Word
MMX Register 1 by MMX Register 2
MMX Register by Memory
0FD1 [11 mm1 mm2] MMX reg 1 [word] <--shift right, shifting in zeroes by MMX reg 2 [word]
0FD1 [mod mm r/m] MMX reg [word] <--shift right, shifting in zeroes by memory[word]
0F71 [11 010 mm] # MMX reg [word] <--shift right, shifting in zeroes by imm[word]
1/1
1/1
1/1
MMX Register by Immediate
PSUBB Subtract Byte With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FF8 [11 mm1 mm2] MMX reg 1 [byte] <---- MMX reg 1 [byte] subtract MMX reg 2 [byte]
0FF8 [mod mm r/m] MMX reg [byte] <---- MMX reg [byte] subtract memory [byte]
1/1
1/1
PSUBD Subtract Dword With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FFA [11 mm1 mm2] MMX reg 1 [dword] <---- MMX reg 1 [dword] subtract MMX reg 2 [dword]
0FFA [mod mm r/m] MMX reg [dword] <---- MMX reg [dword] subtract memory [dword]
1/1
1/1
PSUBSB Subtract Byte Signed With Saturation
MMX Register 2 to MMX Register 1
0FE8 [11 mm1 mm2] MMX reg 1 [sign byte] <--sat-- MMX reg 1 [sign byte] subtract MMX reg 2 [sign
1/1
1/1
byte]
Memory to MMX Register
0FE8 [mod mm r/m] MMX reg [sign byte] <--sat-- MMX reg [sign byte] subtract memory [sign byte]
PSUBSW Subtract Word Signed With Saturation
MMX Register 2 to MMX Register 1
0FE9 [11 mm1 mm2] MMX reg 1 [sign word] <--sat-- MMX reg 1 [sign word] subtract MMX reg 2
1/1
1/1
[sign word]
Memory to MMX Register
0FE9 [mod mm r/m] MMX reg [sign word] <--sat-- MMX reg [sign word] subtract memory [sign word]
PSUBUSB Subtract Byte Unsigned With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FD8 [11 mm1 mm2] MMX reg 1 [byte] <--sat-- MMX reg 1 [byte] subtract MMX reg 2 [byte]
0FD8 [11 mm reg] MMX reg [byte] <--sat-- MMX reg [byte] subtract memory [byte]
1/1
1/1
PSUBUSW Subtract Word Unsigned With Saturation
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FD9 [11 mm1 mm2] MMX reg 1 [word] <--sat-- MMX reg 1 [word] subtract MMX reg 2 [word]
0FD9 [11 mm reg] MMX reg [word] <--sat-- MMX reg [word] subtract memory [word]
1/1
1/1
PSUBW Subtract Word With Wrap-Around
MMX Register 2 to MMX Register 1
Memory to MMX Register
0FF9 [11 mm1 mm2] MMX reg 1 [word] <---- MMX reg 1 [word] subtract MMX reg 2 [word]
0FF9 [mod mm r/m] MMX reg [word] <---- MMX reg [word] subtract memory [word]
1/1
1/1
PUNPCKHBW Unpack High Packed Byte, Data to Packed Words
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F68 [11 mm1 mm2] MMX reg 1 [byte] <--interleave-- MMX reg 1 [up byte], MMX reg 2 [up byte]
0F68 [11 mm reg] MMX reg [byte] <--interleave-- memory [up byte], MMX reg [up byte]
1/1
1/1
PUNPCKHDQ Unpack High Packed Dword, Data to Qword
MMX Register 2 to MMX Register 1
0F6A [11 mm1 mm2] MMX reg 1 [dword] <--interleave-- MMX reg 1 [up dword], MMX reg 2 [up
dword]
1/1
1/1
Memory to MMX Register
0F6A [11 mm reg]
MMX reg [dword] <--interleave-- memory [up dword], MMX reg [up dword]
www.national.com
242
Revision 1.1
NSC [ National Semiconductor ]
