While the x86 core provides maximum compatibility with
the vast amount of internet content available, the intelli-
gent integration of several other functions, such as mem-
ory controller and graphics, offer a true system-level
multimedia solution.
Low typical power consumption:
— 1.0W @ 2.2V/166 MHz
— 2.5W @ 2.9V/266 MHz
Note: Typical power consumption is defined as an aver-
age, measured running Windows at 80% Active
Idle (Suspend-on-Halt) with a display resolution of
800x600x8 bpp @ 75 Hz.
The GXLV processor core is a proven x86 design that
offers competitive performance. It contains integer and
floating point execution units based on sixth-generation
technology. The integer core contains a single, five-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. Accesses to the 16 KB write-back L1
cache are dynamically reordered to eliminate pipeline
stalls when fetching operands.
Speeds offered up to 266 MHz
Unified Memory Architecture:
— Frame buffer and video memory reside in main
memory
— Minimizes Printed Circuit Board (PCB) area require-
ments
— Reduces system cost
In addition to the advanced CPU features, the GXLV pro-
cessor integrates a host of functions typically imple-
mented with external components. A full function graphics
accelerator contains a Video Graphics Array (VGA) con-
troller, bitBLT engine, and a Raster Operations (ROP) unit
for complete Graphical User Interface (GUI) acceleration
under most operating systems. A display controller con-
tains additional video buffering to enable >30 fps MPEG1
playback and video overlay when used with a National
Semiconductor I/O Companion chip such as the CS5530.
Graphics and system memory accesses are supported by
a tightly coupled SDRAM controller which eliminates the
need for an external L2 cache. A PCI host controller sup-
ports up to three bus masters for additional connectivity
and multimedia capabilities.
Compatible with multiple Geode I/O companion
devices provided by National Semiconductor
32-Bit x86 Processor
Supports Intel’s MMX instruction set extension for the
acceleration of multimedia applications
16 KB unified L1 cache
Five-stage pipelined integer unit
Integrated Floating Point Unit (FPU)
Memory Management Unit (MMU) adheres to standard
paging mechanisms and optimizes code fetch perfor-
mance:
The GXLV processor also incorporates Virtual System
Architecture® (VSA™) technology. VSA technology
enables the XpressGRAPHICS and XpressAUDIO sub-
systems. Software handlers are available that provide full
compatibility for industry standard VGA and 16-bit audio
functions that are transparent at the operating system
level.
— Load-store reordering gives priority to memory
reads
— Memory-read bypassing eliminates unnecessary or
redundant memory reads
Re-entrant System Management Mode (SMM)
enhanced for VSA technology
Fully Static Design
The GXLV processor is designed to be used with the
CS5530 I/O Companion, also supplied by National Semi-
conductor. Together they provide a scalable, flexible, low-
power, system-level solution well suited for a wide array of
information appliances ranging from hand-held personal
information access devices to digital set top boxes and
thin clients.
Flexible Power Management
Supports a wide variety of standards:
— APM for Legacy power management
— ACPI for Windows power management
– Direct support for all standard processor (C0-C4)
states
Features
— OnNOW specification compliant
Supports a wide variety of hardware and software
controlled modes:
General Features
— Fully Active
Packaging:
— Active Idle (core stopped, display active)
— Standby (core and all integrated functions halted)
— Sleep (core and integrated functions halted and all
external clocks stopped)
— 352-Terminal Ball Grid Array (BGA) or
— 320-Pin Staggered Pin Grid Array (SPGA)
0.25-micron four layer metal CMOS process
— Suspend Modulation (automatic throttling of CPU
core)
Split rail design:
— Available 2.2V, 2.5V, or 2.9V core
— 3.3V I/O interface (5V tolerant)
– Programmable duty cycle for optimal perfor-
mance/thermal balancing
— Several dedicated and programmable wake-up
events (via Geode I/O companion chip)
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