Electrical Specifications (Continued)
6.5.2.3 Definition of System Conditions for Measuring "On" Parameters
Processor current is highly dependent two functional char-
acteristics, DCLK (DOT clock) and SDRAM frequency.
Table 6-6 shows how these factors are controlled when
measuring the typical average and absolute maximum
processor current parameters.
Table 6-6. System Conditions Used to Determine CPU’s Current Used During the "On" State
System Conditions
CPU Current
Measurement
DCLK
Freq
SDRAM
Freq
VCC2
VCC3
Comments
Typical Average
Nominal
Nominal
50 MHz
Nominal
Note 2
Notes 1 and 4
Absolute Maximum
Max
Max
135 MHz
Max
Notes 3, 4, 5, 7
Note 5
Notes: 1. A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a
display image of vertical stripes (4-pixel wide) alternating between black and white with power manage-
ment disabled.
2. SDRAM nominal frequency represents a single value that the memory controller can be configured for,
between 66 MHz and 78 MHz, based on a given core clock frequency:
166 MHz (5x) / 2.5 = 66.67 MHz
180 MHz (6x) / 2.5 = 72.0 MHz
200 MHz (6x) / 3.0 = 66.67 MHz
233 MHz (7x) / 3.0 = 77.78 MHz
266 MHz (8x) / 3.5 = 76.19 MHz
3. A DCLK frequency of 135 MHz is derived by setting the display mode to 1280x1024x8 bpp at 75 Hz, using
a display image of vertical stripes (1-pixel wide) alternating between black and white with power manage-
ment disabled.
4. See Table 6-4 on page 189 for nominal and maximum voltages.
5. SDRAM max frequency represents the highest frequency that the memory controller can be configured,
up to 100 MHz, based on a given core clock frequency:
166 MHz (5x) / 2.0 = 83.3 MHz
180 MHz (6x) / 2.0 = 90.0 MHz
200 MHz (6x) / 2.0 = 100.0 MHz
233 MHz (7x) / 2.5 = 93.3 MHz
266 MHz (8x) / 3.0 = 88.9 MHz
6. SDRAM speeds between 79 MHz and 100 MHz are only supported for particular types of closed system
designs. Therefore, absolute maximum current will not be realized in most system designs. Refer to the
de-rating curve in Figure 6-3 on page 195 to calculate absolute maximum current based on the system’s
parameters.
7. Not all system designs will support display modes that require a DCLK of 135 MHz. Therefore, absolute
maximum current will not be realized in all system designs. Refer to the de-rating curve in Figure 6-3 on
page 195 to calculate absolute maximum current based on the system’s parameters.
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