Integrated Functions (Continued)
A VGA is made up of several functional units.
pixel comes from bit 7 of each plane, with plane 3 provid-
ing the most significant bit.
•
•
The frame buffer is 256 KB of memory that provides
data for the video display. It is organized as 64 K 32-bit
DWORDs.
pixel[i].bit[j] = dword_fb[address].bit[i*8 + (7-j)]
4.6.1.2 VGA Front End
The sequencer decomposes word and DWORD CPU
accesses into byte operations for the graphics
The VGA front end consists of address and data transla-
tions between the CPU and the frame buffer. This func-
tionality is contained within the graphics controller and
sequencer components. Most of the front end functionality
is implemented in the VGA read and write hardware of the
GXLV processor. An important axiom of the VGA is that
the front end and back end are controlled independently.
There are no register fields that control the behavior of
both pieces. Terms like “VGA odd/even mode” are there-
fore somewhat misleading; there are two different controls
for odd/even functionality in the front end, and two sepa-
rate controls in the refresh path to cause “sensible”
refresh behavior for frame buffer contents written in
odd/even mode. Normally, all these fields would be set up
together, but they don’t have to be. This sort of orthogonal
behavior gives rise to the enormous number of possible
VGA “modes”. The CPU end of the read and write pipe-
lines is one byte wide. Word and DWORD accesses from
the CPU to VGA memory are broken down into multiple
byte accesses by the sequencer. For example, a word
write to A0000h (in a VGA graphics mode) is processed
as if it were two-byte write operations to A0000h and
A0001h.
controller. It also controls a number of miscellaneous
functions, including reset and some clocking controls.
•
The graphics controller provides most of the interface
between CPU data and the frame buffer. It allows the
programmer to read and write frame buffer data in
different formats. Plus provides ROP (raster operation)
and masking functions.
•
•
•
The CRT controller provides video timing signals and
address generation for video refresh. It also provides a
text cursor.
The attribute controller contains the video refresh
datapath, including text rasterization and palette
lookup.
The general registers provide status information for
the programmer as well as control over VGA-host
address mapping and clock selection. This is all
handled in hardware by the graphics pipeline.
It is important to understand that a VGA is constructed of
numerous independent functions. Most of the register
fields correspond to controls that were originally built out
of discrete logic or were part of a dedicated controller
such as the 6845. The notion of a VGA “mode” is a higher-
level convention to denote a particular set of values for the
registers. Many popular programs do not use standard
modes, preferring instead to produce their own VGA set-
ups that are optimal for their purposes.
4.6.1.3 Address Mapping
When a VGA card sees an address on the host bus, bits
[31:15] determine whether the transaction is for the VGA.
Depending on the mode, addresses 000AXXXX,
000B{0xxx}XXX, or 000B{1xxx}XXX can decode into VGA
space. If the access is for the VGA, bits [15:0] provide the
DWORD address into the frame buffer (see odd/even and
Chain 4 modes, next paragraph). Thus, each byte address
on the host bus addresses a DWORD in VGA memory.
4.6.1.1 VGA Memory Organization
The VGA memory is organized as 64K 32-bit DWORDs.
This organization is usually presented as four 64 KB
“planes”. A plane consists of one byte out of every
DWORD. Thus, plane 0 refers to the least significant byte
from every one of the 64K DWORDs. The addressing
granularity of this memory is a DWORD, not a byte; that is,
consecutive addresses refer to consecutive DWORDs.
The only provision for byte-granularity addressing is the
four-byte enable signals used for writes. In C parlance,
On a write transaction, the byte enables are normally
driven from the sequencer’s MapMask register. The VGA
has two other write address mappings that modify this
behavior. In odd/even (Chain 2) write mode, bit 0 of the
address is used to enable bytes 0 and 2 (if zero) or bytes
1 and 3 (if one). In addition, the address presented to the
frame buffer has bit 0 replaced with the PageBit field of
the Miscellaneous Output register. Chain 4 write mode is
similar; only one of the four byte enables is asserted,
based on bits [1:0] of the address, and bits [1:0] of the
frame buffer address are set to zero. In each of these
modes, the MapMask enables are logically ANDed into
the enables that result from the address.
single_plane_byte = (dword_fb[address] >>
(plane * 8)) & 0xFF;
When dealing with VGA, it is important to recognize the
distinction between host addresses, frame buffer
addresses, and the refresh address pipe. A VGA control-
ler contains a lot of hardware to translate between these
address spaces in different ways, and understanding
these translations is critical to understanding the entire
device. In standard four-plane graphics modes, a frame-
buffer DWORD provides eight 4-bit pixels. The left-most
www.national.com
158
Revision 1.1
NSC [ National Semiconductor ]
