Integrated Functions (Continued)
Table 4-29. Display Controller Configuration and Status Registers (Continued)
Bit
Name
VSYE
Description
1
Vertical Sync Enable: Allow generation of the vertical sync signal to a CRT display device:
0 = Disable; 1 = Enable.
When disabled, the VSYNC output will be a static low level. This allows VESA DPMS compliance.
Note that this bit only applies to the CRT; the flat panel VSYNC is controlled by the automatic power
sequencing logic.
0
PPE
Pixel Port Enable: On a low-to-high transition this bit will enable the pixel port outputs.
On a high-to-low transition, this bit will disable the pixel port outputs.
GX_BASE+830Ch-830Fh
DC_OUTPUT_CFG Register (R/W) (Locked)
Reserved: Set to 0.
Default Value = xxx00000h
31:16
15
RSVD
DIAG
Compressed Line Buffer Diagnostic Mode: This bit allows testability of the Compressed Line Buffer via
the diagnostic access registers. A low-to-high transition resets the Compressed Line Buffer write pointer. 0
= Disable (Normal operation); 1 = Enable.
14
CFRW
Compressed Line Buffer Read/Write Select: Enables the read/write address to the Compressed Line
Buffer for use in diagnostic testing of the RAM.
0 = Write address enabled
1 = Read address enabled
13
12
PDEH
PDEL
Pixel Data Enable High:
0 = The PIXEL [17:9] data bus to be driven to a logic low level.
Panel Data Enable Low:
0 = This bit will cause the PIXEL[8:0] data bus to be driven to a logic low level.
Reserved: Set to 0.
11:8
7:5
4:3
2
RSVD
RSVD
RSVD
PCKE
Reserved: Set to 0.
Reserved: Set to 0.
PCLK Enable:
0 = PCLK is disabled and a low logic level is driven off-chip.
1 = Enable PCLK to be driven off-chip.
1
0
16FMT
8-bpp
16-bpp Format: Selects RGB display mode:
0 = RGB 5-6-5 mode
1 = RGB 5-5-5 display mode
This bit is only significant if 8-bpp (OUTPUT_CONFIG, bit 0) is low, indicating 16-bpp mode.
8-bpp / 16-bpp Select:
0 = 16-bpp display mode is selected. 16FMT (OUTPUT_CONFIG, bit 1) will indicate the format of the 16-
bit data.)
1 = 8-bpp display mode is selected. Used in VGA emulation.
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