Index (Continued)
FPU
GP_VGA_LATCH (8214h-8217h)
GP_VGA_READ (8200h-8203h)
GP_VGA_WRITE (8140h-8143h)
Master/Slave Registers
Monochrome Patterns
Pattern Generation
125
124
124
121
122
Mode Control Register
Register Set
Status Register
89
89
89
89
224
228
90
90
90
90
90
90
90
90
89
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
94
Tag Word Register
FPU Instruction Set
Summary Notes
graphics pipeline
Graphics Pipeline Block Diagram
165, 116261
FPU Mode Control Register
Denormalized-operand error exception bit
Divide-by-zero exception bit
Invalid-operation exception bit
Overflow error exception bit
Precision Control Bits
Precision error exception bit
Rounding Control Bits
FPU Operations
120
H
HALT
25
112
High Order Interleaving
I
I/O Address Space
Initialization
Initialization, CPU
Initiator Ready
IRDY
TRDY
Instruction Fields
Instruction Set
60
38
38
FPU Registers
FPU Status Register
Condition code bit 3
27
27
202
39
Condition code bits
Copy of ES bit
Denormalized-operand error exception bit
Divide-by-zero exception bit
Error indicator
Invalid operation exception bit
Overflow error exception bit
Precision error exception bit
Stack Full
eee Field Encoding
Index Field
Memory Addressing
mod base Field Encoding table
mod r/m Field Encoding
Opcode
prefix bytes
reg Field
s-i-b Byte
s-i-b present
204
207
205
207
205
203
203
206
207
207
206
206
207
203
201
202
201
39
Top-of-Stack
Underflow error exception bit
FPU Tag Word Register (TAG7:0]
frame buffer
sreg2 field
sreg3
ss Field
G
Gates
87
40
66
29
94
w Field Operand Size
instruction set
Instruction Set Format Table
Instruction Set Formats
Instruction Set Overview
Instructions
Bit Test Instructions
Exchange Instructions
One-operand Arithmetic and Logical
Two-operand Arithmetic and Logical
Instuction Prefix Summary
Integrated Functions
Integrated Functions Programming Interface
Interleaving
General Purpose Registers
Global Descriptor Table Register (GDTR)
Grant Lines
Graphics Memory (GX_BASE+800000h)
Graphics Pipeline
120–128
120
123
124
122
124
120
124
125
124
121
121
121
122
122
124
124
124
124
122
123
124
123
121
124
125
BitBLT/vector engine
Color Patterns
Diagonal Error Register (108h-810Bh)
Dither Patterns
Error Register (8104-8107h)
GP_BLT_MODE
GP_BLT_MODE (8208h-820Bh)
GP_BLT_STATUS (820Ch-820Fh)
GP_DST/START_Y/XCOOR (8100h-8103h)
GP_DST_XCOOR
GP_DST_YCOOR
GP_INIT_ERROR
GP_PAT_COLOR_0 register
GP_PAT_COLOR_1 (GX_BASE+8112h)
GP_PAT_COLOR_A (8110h)
GP_PAT_COLOR_B (8114h)
GP_PAT_DATA (8120h-812Fh)
GP_RASTER_MODE (8200h-8203h)
GP_RASTER_MODE (GX_BASE+ 8200h)
GP_RASTER_MODE Bit Patterns
GP_SRC_COLOR (810Ch-810Fh)
GP_SRC_COLOR_0 (GX_BASE+810Ch)
GP_SRC_YCOOR
39
39
39
39
203
91
92
Internal Bus Interface
Internal Bus Interface Unit
640KB to 1MB
100–110122
100
100
100
100
100
100
100
102
101
100
100
100
91
C-Bus
FPU Error Support
Graphics
IRQ13
L1 cache
Processor Core
Region Control Field Bit Definitions
Registers (GX_BASE+8000h)
SMI Interrupts
VGA Access
X-Bus
Internal Bus Interface Unit Diagram
Internal Bus Interface Unit Registers
GP_VECTOR_MODE (8204h-8207h)
GP_VGA_BASE (8210h-8213h)
Revision 3.1
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