Index
CCR7
Cyrix Extended MMX Instructions Enable
NMI Enabl
CCR7 Configuration Control Register 7 Index EBh
Clock Mode
A
50
50
50
24
48
48
48
48
48
47
69
87
99
Absolute Maximum Ratings
AC Characteristics
183
186
157
60
73
73
60
60
61
61
73
73
72
74
108
40
Accessing
Address Spaces
Configuration Register Map
Control Registers
Directory Table Entry (DTE)
DTE Cache
I/O Address Space
Memory Address Space
Memory Addressing Modes
Offset Mechanism
Page Frame Offset (PFO)
Page Table Entry (PTE)
Paging Mechanism
Device ID Registers
Graphics/VGA Related Registers
SMM Base Header Address Registers
Configuration Register Summary
Conforming Code Segments
Control Transfer
CPU_READ
CPU_READ/WRITE
EAX instructions
Translation Look-Aside Buffer
Address Translation
Application Register Set
99
99
99
EBX instructions
CPU_WRITE
B
CPUID Instruction
208
208
208
209
210
210
211
211
211
211
208
210
45
46
46
46
46
46
46
45
46
EAX = 0000 0000h
EAX = 0000 0001h
EAX = 0000 0002h
EAX = 8000 0000h
EAX = 8000 0001h
EAX = 8000 0002h
EAX = 8000 0003h
EAX = 8000 0004h
BGA Ball Assignments by Ball Number
BGA Ball Assignments by Pin Name
BGA Ball Assignments Diagram
15
17
14
C
Cache
BB0_BASE
BB0_POINTER
BB1_BASE
BB1_POINTER
GCR register (Index B8h)
L1 cache
scratchpad memory
95
95
95
95
95
95
95
95
95
95
58
69
69
69
69
69
69
EAX = 8000 0005h
CPUID Levels
CPUID Levels, Extended
CR0 Register
Alignment Check Mask
Cache Disable
Emulate Processor Extension
Monitor Processor Extension
Not Write-Through
Numerics Exception
Paging Enable Bit
Protected Mode Enable
Task Switched
Write-back caching
Cache Controller
Cache Disable, bit 30
Cache Test Operations
call gate
Current Privilege Level
Descriptor Privilege Level
Descriptor Privilege Level in Destination
Descriptors Bit Definitions
Segment Selector Field
CCR1
46
46
45
45
45
45
45
Write Protect
CR2 Register
Page Fault Linear Address
CR3 Register
Page Directory Base Register
CR4 Register
System Management Memory Access
CCR1 Configuration Control Register 1 Index C1h
CCR2
49
49
Enable Suspend Pins
Lock NW Bit
Suspend on HALT
49
49
49
49
49
Time Stamp Counter Instruction
45
D
DC Characteristics
Descriptor Bit Structure
Descriptor Types
185
67
87
Write-Through Region 1
CCR2 Configuration Control Register 2 Index C2h
CCR3
Descriptors
Load/Store Serialize 1 GByte to 2 GBytes
Load/Store Serialize 2 GBytes to 3 GBytes
Load/Store Serialize 3 GBytes to 4 GBytes
Map Enable
NMI Enable
SMM Register Lock
49
49
49
49
49
49
49
Gate
gate
Interrupt
Task
67
69
67
67
28
Device Select
DEVSEL
DIMM
28
112
CCR3 Configuration Control Register 3 Index C3h
CCR4
DIR0
Directory Table Entry Cache
Enable CPUID Instruction
I/O Recovery Time
Memory Read Bypassing
SMI Nest
50
50
50
50
50
50
Device ID
51
51
DIR0 Device Identification Register 0 Index FEh
DIR1
Device Identification Revision
DIR1 Device Identification Register 1 Index FFh
51
51
CCR4 Configuration Control Register 4 Index E8h
Revision 3.1
237
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