Instruction Set (Continued)
Table 9-27. Processor Core Instruction Set Summary (Continued)
Real
Mode
Prot’d Real Prot’d
Mode Mode Mode
Flags
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Clock Count
(Reg/Cache Hit)
Instruction
NEG Negate Integer
Opcode
Notes
F [011w] [mod 011 r/m]
x
-
-
-
-
-
-
-
x
-
x
-
x
-
x
-
x
-
1
1
1
1
1
1
b
b
h
h
NOP No Operation
90
-
-
NOT Boolean Complement
OIO Official Invalid Opcode
OR Boolean OR
F [011w] [mod 010 r/m]
0F FF
-
-
-
-
-
-
-
-
1
-
x
0
-
-
-
-
-
8-125
Register to Register
0 [10dw] [11 reg r/m]
0 [100w] [mod reg r/m]
0 [101w] [mod reg r/m]
8 [00sw] [mod 001 r/m] ###
0 [110w] ###
0
-
-
-
x
x
u
x
0
1
1
1
1
1
1
1
1
1
1
b
h
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
OUT Output to Port
Fixed Port
E [011w] #
E [111w]
6 [111w]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
14
15
14/28
14/28
15/29
m
Variable Port
OUTS Output String
b
b
h,m
h,i,j
POP Pop Value off Stack
Register/Memory
8F [mod 000 r/m]
5 [1 reg]
1/4
1
1/4
1
Register (short form)
Segment Register (ES, SS, DS)
Segment Register (FS, GS)
POPA Pop All General Registers
POPF Pop Stack into FLAGS
PREFIX BYTES
[000 sreg2 111]
0F [10 sreg3 001]
61
1
6
1
6
-
-
-
-
-
-
-
-
-
9
9
b
b
h
9D
x
x
x
x
x
x
x
x
x
8
8
h,n
Assert Hardware LOCK Prefix
Address Size Prefix
F0
67
66
-
-
-
-
-
-
-
-
-
m
Operand Size Prefix
Segment Override Prefix
-CS
-DS
-ES
-FS
-GS
-SS
2E
3E
26
64
65
36
PUSH Push Value onto Stack
Register/Memory
FF [mod 110 r/m]
-
-
-
-
-
-
-
-
-
1/3
1
1/3
1
b
h
Register (short form)
5 [0 reg]
Segment Register (ES, CS, SS, DS)
Segment Register (FS, GS)
Immediate
[000 sreg2 110]
1
1
0F [10 sreg3 000]
1
1
6
[10s0] ###
1
1
PUSHA Push All General Registers
PUSHF Push FLAGS Register
RCL Rotate Through Carry Left
Register/Memory by 1
60
9C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
2
11
2
b
b
h
h
D [000w] [mod 010 r/m]
D [001w] [mod 010 r/m]
C [000w] [mod 010 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
3
8
8
3
8
8
b
h
Register/Memory by CL
Register/Memory by Immediate
RCR Rotate Through Carry Right
Register/Memory by 1
D [000w] [mod 011 r/m]
D [001w] [mod 011 r/m]
C [000w] [mod 011 r/m] #
0F 32
x
u
u
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
-
4
8
8
4
8
8
b
h
Register/Memory by CL
Register/Memory by Immediate
RDMSR Read Tmodel Specific Register
RDTSC Read Time Stamp Counter
REP INS Input String
0F 31
-
-
F3 6[110w]
-
-
17+4n 17+4n\
32+4n
b
h,m
REP LODS Load String
REP MOVS Move String
F3 A[110w]
F3 A[010w]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9+2n
9+2n
b
b
h
h
12+2n 12+2n
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