Instruction Set (Continued)
Table 9-27. Processor Core Instruction Set Summary (Continued)
Real
Mode
Prot’d Real Prot’d
Mode Mode Mode
Flags
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Clock Count
(Reg/Cache Hit)
Instruction
LEA Load Effective Address
Opcode
Notes
No Index Register
8D [mod reg r/m]
-
-
-
-
-
-
-
-
-
1
1
1
1
With Index Register
LES Load Pointer to ES
C4 [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
9
b
b
h,i,j
LFS Load Pointer to FS
0F B4 [mod reg r/m]
0F 01 [mod 010 r/m]
0F B5 [mod reg r/m]
0F 01 [mod 011 r/m]
4
9
h,i,j
h,l
LGDT Load GDT Register
LGS Load Pointer to GS
LIDT Load IDT Register
10
4
10
9
b,c
b
h,i,j
h,l
10
10
b,c
LLDT Load LDT Register
From Register/Memory
0F 00 [mod 010 r/m]
-
-
-
-
-
-
-
-
-
8
a
g,h,j,l
LMSW Load Machine Status Word
From Register/Memory
0F 01 [mod 110 r/m]
A [110 w]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
3
11
3
b,c
b
h,l
h
LODS Load String
LSL Load Segment Limit
From Register/Memory
0F 03 [mod reg r/m]
0F B2 [mod reg r/m]
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
9
a
a
g,h,j,p
h,i,j
LSS Load Pointer to SS
4
10
LTR Load Task Register
From Register/Memory
0F 00 [mod 011 r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
4
2
2
2
a
b
g,h,j,l
LEAVE Leave Current Stack Frame
LOOP Offset Loop/No Loop
LOOPNZ/LOOPNE Offset
LOOPZ/LOOPE Offset
C9
4
2
2
2
h
r
E2 +
E0 +
E1 +
r
r
MOV Move Data
Register to Register
8 [10dw] [11 reg r/m]
8 [100w] [mod reg r/m]
8 [101w] [mod reg r/m]
C [011w] [mod 000 r/m] ###
B [w reg] ###
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
1
b
h,i,j
Register to Memory
Register/Memory to Register
Immediate to Register/Memory
Immediate to Register (short form)
Memory to Accumulator (short form)
Accumulator to Memory (short form)
Register/Memory to Segment Register
Segment Register to Register/Memory
MOV Move to/from Control/Debug/Test Regs
Register to CR0/CR2/CR3/CR4
CR0/CR2/CR3/CR4 to Register
Register to DR0-DR3
A [000w] +++
A [001w] +++
8E [mod sreg3 r/m]
8C [mod sreg3 r/m]
0F 22 [11 eee reg]
0F 20 [11 eee reg]
0F 23 [11 eee reg]
0F 21 [11 eee reg]
0F 23 [11 eee reg]
0F 21 [11 eee reg]
0F 26 [11 eee reg]
0F 24 [11 eee reg]
0F 26 [11 eee reg]
0F 24 [11 eee reg]
A [010w]
-
-
-
-
-
-
-
-
-
20/5/5 18/5/6
l
6
10
9
6
10
9
DR0-DR3 to Register
Register to DR6-DR7
10
9
10
9
DR6-DR7 to Register
Register to TR3-5
16
8
16
8
TR3-5 to Register
Register to TR6-TR7
11
3
11
3
TR6-TR7 to Register
MOVS Move String
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
b
b
b
b
h
h
h
h
MOVSX Move with Sign Extension
Register from Register/Memory
MOVZX Move with Zero Extension
Register from Register/Memory
MUL Unsigned Multiply
0F B[111w] [mod reg r/m]
0F B[011w] [mod reg r/m]
F [011w] [mod 100 r/m]
-
-
-
-
-
-
1
1
1
1
-
-
-
-
-
-
Accumulator with Register/Memory
x
x
x
u
u
x
Multiplier:
Byte
Word
4
5
4
5
Doubleword
15
15
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