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10MV5600AX 参数 Datasheet PDF下载

10MV5600AX图片预览
型号: 10MV5600AX
PDF下载: 下载PDF文件 查看货源
内容描述: N沟道FET同步降压稳压器控制器的低输出电压 [N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages]
分类和应用: 稳压器电容器控制器
文件页数/大小: 22 页 / 597 K
品牌: NSC [ National Semiconductor ]
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Rbypass and Cbypass are standard filter components de-  
signed to ensure smooth DC voltage for the chip supply and  
for the bootstrap structure, if it is used. Use 10for the  
resistor and a 2.2µF ceramic for the cap. Cb is the bootstrap  
capacitor, and should be 0.1µF. (In the case of a separate,  
higher supply to the BOOTV pin, this 0.1µF cap can be used  
to bypass the supply.) Using a Schottky device for the boot-  
strap diode allows the minimum drop for both high and low  
side drivers. The On Semiconductor BAT54 or MBR0520  
work well.  
Application Information (Continued)  
In this example, in order to maintain a 2% peak-to-peak  
output voltage ripple and a 40% peak-to-peak inductor cur-  
rent ripple, the required maximum ESR is 6m. Three Sanyo  
10MV5600AX capacitors in parallel will give an equivalent  
ESR of 6m. The total bulk capacitance of 16.8mF is  
enough to supply even severe load transients. Using the  
same capacitors for both input and output also keeps the bill  
of materials simple.  
Rp is a standard pull-up resistor for the open-drain power  
good signal, and should be 10k. If this feature is not  
necessary, it can be omitted.  
RCS is the resistor used to set the current limit. Since the  
design calls for a peak current magnitude (Io + 0.5 * Io) of  
12A, a safe setting would be 15A. (This is well below the  
saturation current of the output inductor, which is 25A.)  
Following the equation from the Current Limit section, use a  
3.3kresistor.  
RFADJ is used to set the switching frequency of the chip.  
Following the equation in the Theory of Operation section,  
the closest 1% tolerance resistor to obtain fSW = 300kHz is  
88.7k.  
MOSFETS  
MOSFETS are a critical part of any switching controller and  
have a direct impact on the system efficiency. In this case  
the target efficiency is 85% and this is the variable that will  
determine which devices are acceptable. Loss from the ca-  
pacitors, inductors, and the LM2727 itself are detailed in the  
Efficiency section, and come to about 0.54W. To meet the  
target efficiency, this leaves 1.45W for the FET conduction  
loss, gate charging loss, and switching loss. Switching loss  
is particularly difficult to estimate because it depends on  
many factors. When the load current is more than about 1 or  
2 amps, conduction losses outweigh the switching and gate  
charging losses. This allows FET selection based on the  
RDSON of the FET. Adding the FET switching and gate-  
charging losses to the equation leaves 1.2W for conduction  
losses. The equation for conduction loss is:  
CSS depends on the users requirements. Based on the  
equation for CSS in the Theory of Operation section, for a  
3ms delay, a 12nF capacitor will suffice.  
EFFICIENCY CALCULATIONS  
A reasonable estimation of the efficiency of a switching  
controller can be obtained by adding together the loss is  
each current carrying element and using the equation:  
PCnd = D(I2 * RDSON *k) + (1-D)(I2 * RDSON *k)  
o
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The factor k is a constant which is added to account for the  
increasing RDSON of a FET due to heating. Here, k = 1.3. The  
Si4442DY has a typical RDSON of 4.1m. When plugged into  
the equation for PCND the result is a loss of 0.533W. If this  
design were for a 5V to 2.5V circuit, an equal number of  
FETs on the high and low sides would be the best solution.  
With the duty cycle D = 0.24, it becomes apparent that the  
low side FET carries the load current 76% of the time.  
Adding a second FET in parallel to the bottom FET could  
improve the efficiency by lowering the effective RDSON. The  
lower the duty cycle, the more effective a second or even  
third FET can be. For a minimal increase in gate charging  
loss (0.054W) the decrease in conduction loss is 0.15W.  
What was an 85% design improves to 86% for the added  
cost of one SO-8 MOSFET.  
The following shows an efficiency calculation to complement  
the Circuit of Figure 3. Output power for this circuit is 1.2V x  
10A = 12W.  
Chip Operating Loss  
PIQ = IQ-V *VCC  
CC  
2mA x 5V = 0.01W  
FET Gate Charging Loss  
PGC = n * VCC * QGS * fOSC  
The value n is the total number of FETs used. The Si4442DY  
has a typical total gate charge, QGS, of 36nC and an rds-on of  
4.1m. For  
a
single FET on top and bottom:  
CONTROL LOOP COMPONENTS  
2*5*36E-9*300,000 = 0.108W  
The circuit is this design example and the others shown in  
the Example Circuits section have been compensated to  
improve their DC gain and bandwidth. The result of this  
compensation is better line and load transient responses.  
For the LM2727, the top feedback divider resistor, Rfb2, is  
also a part of the compensation. For the 10A, 5V to 1.2V  
design, the values are:  
FET Switching Loss  
PSW = 0.5 * Vin * IO * (tr + tf)* fOSC  
The Si4442DY has a typical rise time tr and fall time tf of 11  
and 47ns, respectively. 0.5*5*10*58E-9*300,000 = 0.435W  
Cc1 = 4.7pF 10%, Cc2 = 1nF 10%, Rc = 229k1%. These  
values give a phase margin of 63˚ and a bandwidth of  
29.3kHz.  
SUPPORT CAPACITORS AND RESISTORS  
The Cinx capacitors are high frequency bypass devices,  
designed to filter harmonics of the switching frequency and  
input noise. Two 1µF ceramic capacitors with a sufficient  
voltage rating (10V for the Circuit of Figure 3) will work well  
in almost any case.  
www.national.com  
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