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10MV5600AX 参数 Datasheet PDF下载

10MV5600AX图片预览
型号: 10MV5600AX
PDF下载: 下载PDF文件 查看货源
内容描述: N沟道FET同步降压稳压器控制器的低输出电压 [N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages]
分类和应用: 稳压器电容器控制器
文件页数/大小: 22 页 / 597 K
品牌: NSC [ National Semiconductor ]
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until VCC rises above 4.2V. As with shutdown, the soft start  
capacitor is discharged through a FET, ensuring that the next  
start-up will be smooth.  
Application Information (Continued)  
CURRENT LIMIT  
Current limit is realized by sensing the voltage across the  
low side FET while it is on. The RDSON of the FET is a known  
value, hence the current through the FET can be determined  
as:  
MOSFET GATE DRIVERS  
The LM2727/37 has two gate drivers designed for driving  
N-channel MOSFETs in a synchronous mode. Power for the  
drivers is supplied through the BOOTV pin. For the high side  
gate (HG) to fully turn on the top FET, the BOOTV voltage  
must be at least one VGS(th) greater than Vin. (BOOTV ≥  
2*Vin) This voltage can be supplied by a separate, higher  
voltage source, or supplied from a local charge pump struc-  
ture. In a system such as a desktop computer, both 5V and  
12V are usually available. Hence if Vin was 5V, the 12V  
supply could be used for BOOTV. 12V is more than 2*Vin, so  
the HG would operate correctly. For a BOOTV of 12V, the  
initial gate charging current is 2A, and the initial gate dis-  
charging current is typically 6A.  
VDS = I * RDSON  
The current limit is determined by an external resistor, RCS  
,
connected between the switch node and the ISEN pin. A  
constant current of 50µA is forced through Rcs, causing a  
fixed voltage drop. This fixed voltage is compared against  
VDS and if the latter is higher, the current limit of the chip has  
been reached. RCS can be found by using the following:  
RCS = RDSON(LOW) * ILIM/50µA  
For example, a conservative 15A current limit in a 10A  
design with a minimum RDSON of 10mwould require a  
3.3kresistor. Because current sensing is done across the  
low side FET, no minimum high side on-time is necessary. In  
the current limit mode the LM2727/37 will turn the high side  
off and the keep low side on for as long as necessary. The  
chip also discharges the soft start capacitor through a fixed  
95µA source. In this way, smooth ramping up of the output  
voltage as with a normal soft start is ensured. The output of  
the LM2727/37 internal error amplifier is limited by the volt-  
age on the soft start capacitor. Hence, discharging the soft  
start capacitor reduces the maximum duty cycle D of the  
controller. During severe current limit, this reduction in duty  
cycle will reduce the output voltage, if the current limit con-  
ditions lasts for an extended time.  
20049402  
During the first few nanoseconds after the low side gate  
turns on, the low side FET body diode conducts. This causes  
an additional 0.7V drop in VDS. The range of VDS is normally  
much lower. For example, if RDSON were 10mand the  
current through the FET was 10A, VDS would be 0.1V. The  
current limit would see 0.7V as a 70A current and enter  
current limit immediately. Hence current limit is masked dur-  
ing the time it takes for the high side switch to turn off and the  
low side switch to turn on.  
FIGURE 1. BOOTV Supplied by Charge Pump  
In a system without a separate, higher voltage, a charge  
pump (bootstrap) can be built using a diode and small ca-  
pacitor, Figure 1. The capacitor serves to maintain enough  
voltage between the top FET gate and source to control the  
device even when the top FET is on and its source has risen  
up to the input voltage level.  
UVP/OVP  
The LM2727/37 gate drives use a BiCMOS design. Unlike  
some other bipolar control ICs, the gate drivers have rail-to-  
rail swing, ensuring no spurious turn-on due to capacitive  
coupling.  
The output undervoltage protection and overvoltage protec-  
tion mechanisms engage at 70% and 118% of the target  
output voltage, respectively. In either case, the LM2727 will  
turn off the high side switch and turn on the low side switch,  
and discharge the soft start capacitor through a MOSFET  
switch. The chip remains in this state until the shutdown pin  
has been pulled to a logic low and then released. The UVP  
function is masked only during the first charging of the soft  
start capacitor, when voltage is first applied to the VCC pin. In  
contrast, the LM2737 is designed to continue operating dur-  
ing UVP or OVP conditions, and to resume normal operation  
once the fault condition is cleared. As with the LM2727, the  
powergood flag goes low during this time, giving a logic-level  
warning signal.  
POWER GOOD SIGNAL  
The power good signal is the or-gated flag representing  
over-voltage and under-voltage protection. If the output volt-  
age is 18% over it’s nominal value, VFB = 0.7V, or falls 30%  
below that value, VFB = 0.41V, the power good flag goes low.  
The converter then turns off the high side gate, and turns on  
the low side gate. Unlike the output (LM2727 only) the power  
good flag is not latched off. It will return to a logic high  
whenever the feedback pin voltage is between 70% and  
118% of 0.6V.  
SHUT DOWN  
UVLO  
If the shutdown pin SD is pulled low, the LM2727/37 dis-  
charges the soft start capacitor through a MOSFET switch.  
The high side switch is turned off and the low side switch is  
turned on. The LM2727/37 remains in this state until SD is  
released.  
The 4.2V turn-on threshold on VCC has a built in hysteresis  
of 0.6V. Therefore, if VCC drops below 3.6V, the chip enters  
UVLO mode. UVLO consists of turning off the top FET,  
turning on the bottom FET, and remaining in that condition  
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