CF5020 series
PAD LAYOUT
(Unit:
µ
m)
(900,1050)
VDD
Q
Y
HA5020
NPC
VSS
INHN
(0,0)
XT XTN
X
Chip size: 0.9
×
1.05mm
Chip thickness: 220µm ± 30µm
PAD size: 90µm
Chip base: V
DD
level
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Name
I/O
Description
X
INHN
XT
XTN
VSS
Q
VDD
I
I
O
–
O
–
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
Amplifier input
Amplifier output
(–) ground
Output
(+) supply voltage
Crystal connection pins.
Crystal is connected between XT and XTN.
144.6
347.8
560.6
755.4
755.4
151.4
Y
190.6
171
171
497.8
905.4
918.2
BLOCK DIAGRAM
VDD VSS
XTN
C
G
R
f 1
C
f
C
D
R
D
XT
R
f 2
Q
INHN
INHN = LOW active
NIPPON PRECISION CIRCUITS INC.—2