5042 series
PAD LAYOUT
(Unit: µm)
(420,345)
VSS
4
3
Q
5
6
VDD
INHN
Y
(0,0)
1
2
(−420,−345)
XTN
XT
X
Chip size: 0.84mm × 0.69mm
Chip thickness: 130µm 15µm
Pad size: 80µm × 80µm
Chip base: V level
SS
PAD DIMENSIONS PIN DESCRIPTION
Pad dimensions [µm]
Pad No.
Pin
I/O
Name
Description
X
Y
1
2
XTN
XT
O
I
Amplifier output
Amplifier input
–225.2
225.2
–253.5
–253.5
Crystal connection pins.
Crystal is connected between XT and XTN.
High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
3
4
INHN
VSS
I
Output state control input
(–) ground
328.5
328.5
–5.0
–
–
223.8
Output frequency determined by internal circuit
to one of f , f /2, f /4, f /8, f /16, f /32.
High impedance in standby mode
5
6
Q
O
–
Output
–328.5
–328.5
223.8
–5.0
O
O
O
O
O
O
VDD
(+) supply voltage
–
BLOCK DIAGRAM
XT
XTN
RV
RV
Regulator*2
RF
VDD
1
N *1
Q
Oscillation
Detection
INHN
VSS
Temperature
Compensation
FO, TO, RTG, TLO, TLG,
THO, THG
Control Register
*1. N = 1, 2, 4, 8, 16, 32 (mask option)
*2. 5042A×A version only
SEIKO NPC CORPORATION—3
NPC [ NIPPON PRECISION CIRCUITS INC ]
