WF5028 series
PAD LAYOUT
(Unit: µm)
ꢀ WF5028A×
ꢀ CF5028B×
(for Wire Bonding (type I))
ꢀ CF5028C×
(for Wire Bonding (type II))
(for Flip Chip Bonding)
(750,690)
Q
(750,690)
(750,690)
VSS
5
6
4
3
Q
5
6
4
3
VSS
VDD
5
6
4
3
Q
Y
Y
Y
INHN
INHN
VDD
VDD
INHN
VSS
1
2
1
2
1
2
(0,0)
(0,0)
(0,0)
XT
XTN
XTN
XT
XT
XTN
X
X
X
Chip size: 0.75 × 0.69mm
Chip thickness: 1ꢀ0 15ꢁm
Chip size: 0.75 × 0.69mm
Chip thickness: 1ꢀ0 15ꢁm
PAD size: 90ꢁm
Chip size: 0.75 × 0.69mm
Chip thickness: 1ꢀ0 15ꢁm
PAD size: 90ꢁm
Chip base: V level
PAD size: 90ꢁm
Chip base: V level
Chip base: V level
SS
SS
SS
PAD DIMENSIONS PIN DESCRIPTION
Pad dimensions [µm]
Pad No.
Pad No.
Pin
Name
Description
X
Y
5028A× 5028B× 5028C×
1
2
ꢀ
229
520
6ꢀ6
114
114
ꢀ04
1
2
ꢀ
2
1
6
1
2
5
XT
Amplifier input
Amplifier output
Crystal connection pins. Crystal is connected
between XT and XTN.
XTN
VDD (+) supply voltage
–
Output frequency determined by internal circuit
to one of f , f /2, f /4, f /8, f /16, f /ꢀ2, f /64
4
5
6
6ꢀ6
114
114
5ꢀ1
5ꢀ1
ꢀ04
4
5
6
5
4
ꢀ
4
ꢀ
6
Q
Output
O
O
O
O
O
O
O
VSS
INHN
(–) ground
–
Output state
control input
High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
BLOCK DIAGRAM
VDD VSS
INHN
RF
DIVIDER
CMOS
Q
XT
RD
CG
CD
XTN
SEIKO NPC CORPORATION —3