74LVC74A-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aaf615
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 k
1 k
500
500
500
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
74LVC74A_Q100
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 5 April 2013
11 of 18
NEXPERIA [ Nexperia ]
