Nexperia
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
4 Functional diagram
1
2
&
&
&
&
3
6
4
5
1
2
1A
1B
3
6
1Y
2Y
4
5
2A
2B
9
8
10
9
3A
3B
3Y
8
10
A
12
13
12
13
4A
4B
11
4Y
11
Y
B
mna222
mna223
mna221
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3. IEC logic symbol
5 Pinning information
5.1 Pinning
74HC08-Q100
74HCT08-Q100
terminal 1
index area
1B
2
3
4
5
6
13 4B
12 4A
74HC08-Q100
74HCT08-Q100
1Y
2A
2B
2Y
11
4Y
10 3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
(1)
GND
4B
4A
4Y
3B
3A
3Y
9
1Y
aaa-004039
Transparent top view
2A
2B
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
2Y
8
GND
aaa-004038
Figure 4. Pin configuration SO14 and TSSOP14
Figure 5. Pin configuration DHVQFN14
74HC_HCT08_Q100
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 13 June 2017
2 / 15
NEXPERIA [ Nexperia ]
